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march 2009 rev 2 1/167 1 stv82x8 digital audio decoder/processor for btsc television/video recorders features fully automatic mult i-standard demodulation ? m/n standards ? fm mono ? btsc (us mts) stereo and sap standards multi-channel capability ? 3 x i2s digital inputs ?i2s src ? s/pdif (pass thru/out) ? 5.1 analog outputs ? 1 x i2s digital output (shared with one i2s digital input) ? 2 x i2s additional digital outputs (tqfp100 only) ? i2s digital loop for external delay (tqfp100 only) sound processing: loudspeaker ?dolby ? ? pro logic ? ? ?dolby ? ?? pro logic ii ? ? ? st royalty-free processing: st widesurround tm , st omnisurround tm , (which is virtual dolby ? ? surround and virtual dolby ? ? digital compliant), st dynamic bass tm ?srs ? ? wow tm , srs ? trusurround xt tm , (which is virtual dolby ? ? surround and virtual dolby ? ? digital compliant) ? svc (smart volume control), 5-band equalizer and loudness ? independent volume/balance ? variable beep tone and 3 sampled tones sound processing: headphone ? svc (smart volume control), bass-treble, loudness and srs ? ? trubass tm , ? independent volume/balance analog audio matrix ? 4 stereo inputs or 5 stereo inputs (tqfp100 only) ? 3 stereo outputs ? thru mode ?2 v rms capability audio delay for audio video synchronization ? embedded stereo delay up to 117 ms for lip- sync function ? independent delay on headphone and loudspeaker channels ? external additional audio delay support (tqfp100 only) description the stv82x8 family, based on 24-bit 48khz audio dsps (digital signal proces sors), performs high quality and advanced dedicated digital audio processing.the stv82x8 devices provide all of the necessary resources for automatic detection and demodulation of analog audio transmissions for usa, taiwanese, and brazilian terrestrial analog tv broadcasts. virtual or true multi-channel capabilities and easy digital links make them ideal for digital audio low cost consumer applications. starting from enhanced stereo up to independent control of 5 loudspeakers and a subwoofer (5.1 channels), the stv82x8 family offers standard and advanced features plus sound enhancements, spatial and virtual effects to enhance television viewer comfort and entertainment. table 1. device summary order code packaging stv82x8 tray tqfp80 package ? s t v 8 2 x 8 tqfp100 package ? s t v 8 2 x 8 www.st.com www.datasheet.co.kr datasheet pdf - http://www..net/
contents stv82x8 2/167 contents 1 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 digital signal processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 back-end processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 st widesurround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 st omnisurround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 dolby pro logic ii decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6.1 bass management configuration 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6.2 bass management configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6.3 bass management configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.4 bass management configuration 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.5 bass management configuration 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.6 bass management configuration 5 (stereo full bandwidth speakers) . . 16 2.6.7 bass management configuration 6 (stereo narrow bandwidth speakers) . 16 2.7 srs wow and trusurround xt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.1 srs trusurround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.2 srs wow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8 svc (smart volume control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 st dynamic bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10 5-band audio equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10.1 bass/treble control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10.2 automatic loudness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11 volume/balance control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12 soft mute control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.13 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.14 internal audio/video delay (lip sync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.15 scartaux channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 analog audio matrix (input/output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 contents 3/167 4 i2s interface (input/output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 i2s inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 i2s inputs in tqfp 80 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 i2s inputs in tqfp 100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 i2s outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.1 i2s outputs in tqfp 80 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.2 i2s outputs in tqfp 100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 s/pdif input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 standby mode (loop-through mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 additional controls and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 headphone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 irq generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3 i2c bus expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 stv82x8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1 i2c address and protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2 start-up and configuration change procedure . . . . . . . . . . . . . . . . . . . . . 35 9.3 process flow during patch loading and dsp initialization . . . . . . . . . . . . . 38 9.4 input configuration change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1 i2c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2 software registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 stv82x8 general control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4 clocking 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5 demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.6 demodulator channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.7 i2s and analog control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 www.datasheet.co.kr datasheet pdf - http://www..net/
contents stv82x8 4/167 10.8 clocking 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.9 dsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.10 automatic standard recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.11 demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.12 audio preprocessing and selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.13 matrixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.14 audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.15 mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.16 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.17 spdif output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.18 headphone configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10.19 dac control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.20 autostandard coefficients settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.1 tqfp 80-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.2 tqfp 100-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13 input/output groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 14 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.1 stv82x8 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.1.1 core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.1.2 software information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.1.3 electrical features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 16 digital demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 16.1 sound if signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 16.2 demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 17 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 contents 5/167 17.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 17.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 17.3 power supply data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 17.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 17.5 analog sound if signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 17.6 sif to i2s output path characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 17.7 scart to scart analog path characteristics . . . . . . . . . . . . . . . . . . . 156 17.8 scart and mono in to i2s path characteristics . . . . . . . . . . . . . . . . . 157 17.9 i2s to ls/hp/sub/c path characteristics . . . . . . . . . . . . . . . . . . . . . . . . 157 17.10 i2s to scart path characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 17.11 mute characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 17.12 digital i/os characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 17.13 i2c bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 17.14 i2s bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 18 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18.1 tqfp80 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 18.2 tqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 18.3 environmentally-friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 19 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 20 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 www.datasheet.co.kr datasheet pdf - http://www..net/
block diagrams stv82x8 6/167 1 block diagrams figure 1. stv82x8 block diagram (tqfp80) ls_c ls_sub output analog audio matrix input analog audio matrix audio a/d i2c clock generator headphone volume, balance, loudness smart volume control loudspeakers delay, equalizer, loudness st widesurround, st dynamic bass, smart volume control, audio matrix back-end processing and pre-scaler automatic agc btsc digital irq s/pdif in detection sc1_in_l ls_l headphone hp_lss_l scl sda sif bass management, bip tones srs? wow? or trusurround? digital audio processing srs ? trubass? decoder audio dac a/d 0.9 vrms 2vrms digital audio processing mono_in sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r sc4_in_l sc4_in_r clk_sel xtalin xtalout sc1_out_l sc1_out_r sc2_out_l sc2_out_r sc3_out_l sc3_out_r hp_lss_r ls_r dolby? pro logic? i2c dolby? pro logic ii?, st omnisurround audio dac 0.9 vrms 0.9 vrms audio dac stereo audio st dynamic bass, bass/treble volume balance mute 2vrms 2vrms matrix s/pdif out i2s interface s_clk data_0 data_1 data_2 interface detection & smart control lr_clk o_pcm_clk i2s inputs/output dac headphone/ surround loudspeakers scart outputs mono input sound if scart inputs www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 block diagrams 7/167 figure 2. stv82x8 block diagram (tqfp100) ls_c ls_sub output analog audio matrix input analog audio matrix audio a/d i2c clock generator headphone delay,bass/treble, loudness, smart volume control, loudspeakers delay, equalizer, loudness st widesurround, st dynamic bass, smart volume control, audio matrix back-end processing and pre-scaler automatic agc btsc digital irq s/pdif in detection sc1_in_l ls_l headphone hp_lss_l scl sda sif1 bass management, bip tones srs? wow? or trusurround xt? digital audio processing srs? trubass?, decoder audio dac a/d 0.9 vrms 2vrms digital audio processing mono_in sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r sc4_in_l sc4_in_r clk_sel xtalin xtalout sc1_out_l sc1_out_r sc2_out_l sc2_out_r sc3_out_l sc3_out_r hp_lss_r ls_r dolby? pro logic? i2c dolby? pro logic ii?, st omnisurround sc5_in_l sc5_in_r audio dac 0.9 vrms 0.9 vrms audio dac sif2 st dynamic bass, bip tones volume balance mute 2vrms 2vrms matrix o_data_0 o_data_1 o_lr_clk o_sclk pcm_clk s/pdif out i2s interface sclk lr_clk data_0 data_1 data_2 interface detection & smart control i2s inputs/outputs d_data stereo audio dac i2s outputs loudspeakers headphone/ surround scart outputs sound if mono input scart inputs www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 8/167 2 digital signal processor a dedicated dsp (digital signal processor) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. the internal 24-bit architecture will ensure a high quality signal treatment and an excellent dynamic. figure 3. stv82x8 audio processing (front-end) 2.1 back-end processing the ?back-end? processing corresponds to the low frequency signal processing (32 khz or higher frequencies) of the demodulat or and other inputs (i2s, adc). figure 4 shows a flowchart of the back-end processing tasks. however, the figure shows that the processing is only a single sour ce processing flow (no processing is demodulator i2s0 input scart ad dc removal dc removal deemphasis 25/50/75us deemphasis 25/50/75us dbx decoder fine prescale src 96k->48k stereo dematrix - btsc dc removal i2s1 input src 24~50khz->48k i2s2 input 24~50khz multi-ch 48khz delay 2ch. peak demod prescale i2s prescale detector scart prescale dolby downmix main sources matrix 0 1 2 5 3 4 a b c d e f lt/rt (only in multi i2s input mode) pre post www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 9/167 possible with ?demod + scart? and i2s inputs simultaneously) and that the selection of a headphone output restricts the loudspeakers configuration to 2.1 instead of 5.1. figure 4. stv82x8 audio processing (back-end) delay srs trubass st dynamic bass 5 ch. s.v.c. 2 ch. s.v.c. 5 bands eq. bass-treble or 5 ch. loudness 2 ch. loudness st dynamic bass bass-treble srs tr ub a s s 5 ch. balance volume with master control 2 ch. balance mute volume mute beeper beeper bass managt 2 ch. balance volume mute ls channel matrix dolby prologic 2 with pinknoise generator tr u s r n d xt st omnisrnd st wide srnd main sources matrix 0 1 2 5 3 4 a b c d e f 2 ch. balance volume mute dac copy hp channel matrix scart channel matrix spdif channel matrix scartaux channel matrix hp channel matrix scart channel matrix spdif channel matrix scartaux channel matrix hp channel matrix scart channel matrix spdif channel matrix scaraux channel matrix hp copy cm_position = 0 cm_position = 1 cm_position = 3 ls delay hp l/r dac c/sub dac srnd/hp dac scart dac spdif scartaux i2s out delay (hp) hp channel matrix scart channel matrix spdif channel matrix scartaux channel matrix cm_position = 2 2 ch. mute i2s0_ data0 i2s0_ data1 i2s_ data0 www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 10/167 the main features depend on the path: fm channel ?dc removal ? prescaling ? de-emphasis (50 or 75 us) ? stereo dematrix input scart channel ?dc removal ? prescaling input i2s channel ? i2s prescaling digital audio matrix ? audio channel multiplexer between the differ ent sources (if, i2s, scart) towards all outputs (s/pdif, ls, hp or scart). autostandard management ? device configuration depending on the standard to be detected ? freeze the device when a standard is detected ? once a standard detected, check that there is no change in the detection status ? set the correct action depending on any change in the detection status (mono backup or mute setup and new standard detection) scart ? downmixing: l t / r t or l 0 / r 0 (see ac-3 specification) ? soft mute 2.2 audio processing the following software is provided for main loudspeakers (l, r, c, l s , r s , subw): downmix dolby ? pro logic ii ? decoder (l t , r t l, r, c, ls, rs, subw) with bass management st widesurround tm , st omnisurround tm , srs ? wow tm or srs ? trusurround xt tm (certified virtual dolby ? surround and virtual dolby ? digital) st dynamic bass tm svc (smart volume control) 5-band equalizer or bass-treble loudness volume with independent channels (smooth volume control) master volume control mute/soft-mute balance beeper pink noise generator (used to position the loudspeakers) programmable delay for each loudspeaker adjustable delay for ?lip sync? up to 120 ms (to compensate for audio/video latency) www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 11/167 the following software is provided for the headphone or auxiliary output: downmix srs ? trubass tm st dynamic bass tm svc (smart volume control) bass/treble loudness independent volume for each channel (smooth volume control) soft mute balance beeper adjustable delay for ?lip sync? feature up to 120 ms (to compensate for audio/video latency) the following software is provided for scart or s/pdif outputs: downmix soft mute 2.3 st widesurround stv82x8 offers three preset st widesurround tm sound effects on the loudspeakers path: music, a concert hall effects movie, for films on tv simulated stereo, which generates a pseudo-stereo effect from mono source ?st widesurround? sound is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. this could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for normal home use. the st widesurround system exploits a method of phase shifting to achieve a similar result using only two speakers. it restores spatiality by adding artificial phase differences. the surround/pseudo-stereo mode is automatically selected by the automatic standard recognition system (autostandard) depending on t he detected stereo or mono source. by default, ?movie? is selected for surround mode. this value can be changed to ?music? by the widesrnd_mode bit in the widesrnd_control register. additional user controls are provided to better adapt the spatial effect to the source. the st widesurround gain ( widesrnd_level ) and st widesurround frequency ( widesrnd_freq ) registers can be used to enhance music predominancy in music mode and theater effect and voice predominancy in movie mode. 2.4 st omnisurround stv82x8 offers a spatial virtualizer st omnisurround tm to output any multi-channel input in stereo on the loudspeakers path. www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 12/167 ?st omnisurround? recreates a multi-channel spatial sound environment using only the left and right front speakers. it can be adapted to any input configuration (omnisrnd_input_mode). st voice allows you to enhance the voice content of your program to increase the intelligibility and the presence of the sound. 2.5 dolby pro logic ii decoder dolby ? pro logic ii ? is a matrix decoder that decodes the five channels of surround sound that have been encoded onto the stereo sound tracks of dolby ? surround program material such as dvd movies and tv shows. it is even possible to decode standard stereo signals like music or non encoded movies. furthermore, it is an active process designed to enhance sound localization through the use of very high-separation decoding techniques. the dolby ? pro logic ii ? decoder is also able to emulate the former dolby ? pro logic ? decoder in a specific mode. 2.6 bass management the base management process generates the s ubwoofer signal and adjusts all loudspeaker channels gain and bandwidth. speakers capable of reproducing the entire frequency range will be referred to as ?full range speakers?, then signals sent to full range speaker will be full bandwidth (no filtering). speakers that have limited bass handling capabilities will be referred to as ?satellite speakers?, then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 hz. in the stv82x8, seven output configuration modes have been implemented according to ?dolby digital consumer decoder? specifications. they are described in the following paragraphs: 2.6.1 bass management configuration 0 in some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. the output configuration shown in figure 5 offers this possibility. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 13/167 figure 5. bass management configuration 0 (wit h pro logic switch indicating its reset state) 2.6.2 bass management configuration 1 configuration 1, shown in figure 6 , assumes that all five speakers are not full range and that all of the bass information is redirected to and reproduced by a single subwoofer. this configuration is intended for use with five satellite speakers. to prevent signal overload, the five main channels are attenuated by 15 db, while the lfe channel is attenuated by 5db to maintain the proper mixing ratio. figure 6. bass management configuration 1 (wit h pro logic switch indicating its reset state) r l c ls rs lfe l r c ls rs subw + -15 db -5 db pro logic off switch r l c ls rs lfe l r c ls rs subw pro logic off switch + -5 db -15 db www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 14/167 2.6.3 bass management configuration 2 configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. also, all bass data is redirected to the left and right speakers. this configuration includes output level adjustment that allows 12 db attenuation for the three smaller speakers (c, ls, rs). when the level adjustment is disabled the decoder boosts the full range speakers (left, right) by 12 db. figure 7. bass management configuration 2 (all switches indicate their reset state) 2.6.4 bass management configuration 3 the third configuration, shown in figure 8 , assumes that all speakers except the center are full range, then all bass information is directed to and reproduced by the front left and front right speakers and both surround speakers. to provide more flexibility to this configuration, a subwoofer switch offers an option which produces a subwoofer channel by the lfe channel. when the subwoofer switch is off, the input channels are attenuated by 8 db. configuration 3 is required in certain high-end products. subw c l r ls rs lfe l c r ls rs + + + + level adjustment off switch subwoofer on switch pro logic off switch +12 db -1.5 db -12 db +12 db -12 db -12 db -1.5 db -12 db -12 db -15 db -5 db www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 15/167 figure 8. bass management configuration 3 (all switches indicate their reset state) 2.6.5 bass management configuration 4 this configuration implements the simplified dolby ? configuration. the center, left surround and right surround channels are summed and then filtered by the lpf. the composite bass information is either summed back into the left and right channels or summed with the lfe channel and sent to the subwoofer output, see figure 9 . c l r ls rs l c r ls rs subw lfe -4db + + + + -8db -4db -8db -4db -8db -4db -8db -4db -8db -4db -8db + + +10db +8db +4db +8db +4db +8db +4db +8db +4db +8db +4db subwoofer on switch subwoofer on switch level adjustment off switch -4.5db www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 16/167 figure 9. implementation of bass management configuration 4 (simplified configuration) 2.6.6 bass management configuratio n 5 (stereo full bandwidth speakers) this configuration is dedicated to stereo applications implementing full bandwidth speakers. figure 10. implementation of bass management configuration 5 (stereo full bandwidth speakers) 2.6.7 bass management configuration 6 (stereo narrow bandwidth speakers) this configuration is dedicated to stereo applications implementing narrow bandwidth speakers and subwoofer. c l r ls rs l c r ls rs + + + subw lfe pro logic off switch -5db -10.5db + -4.5db subwoofer on switch r l l (wide) r (wide) subwoofer -5db sw -6db lfe + www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 17/167 figure 11. implementation of bass management configuration 6 (stereo narrow bandwidth speakers) 2.7 srs wow and trusurround xt the srs ? trusurround xt tm is a processing system that can accept from 1 to 6 channels on input and that will generate a 2-channel output signal. this processing system includes the latest srs? algorithms: srs ? wow tm srs ? trusurround? (multi-channel signal virtualizer) 2.7.1 srs trusurround the srs ? trusurround ? is a processing that can accept from 2 to 5 channels on input and that will generate a 2-channel output signal. srs ? trusurround ? uses hrtf (head-related transfer function) -based frequency tailoring of (l/r) difference signals to extend the sound image out past the physical boundaries of the speaker placements to surround channel information. these rear channel hrtf curves have much greater peak to valley differences at center frequencies. these cause rear channel difference signals that virtualize farther behind the listener directed to a different virtual position as compared to front channel signals. information that is equal (l+r) in the rear surround channels is processed by an identical hrtf curve but mixed in at a much lower amount. this hrtf processing of equal (l/r) signals is used to virtualize information to the rear of the listener. the srs ? trusurround ? is certified by dolby laboratories to be a virtual dolby ? digital and virtual dolby ? surround. r l l (narrow) r (narrow) subwoofer -5db sw + -6db lfe www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 18/167 2.7.2 srs wow the srs ? wow tm is a sound processing system including: srs ? 3d mono/stereo tm srs ? dialog clarity tm srs ? trubass tm srs 3d mono/stereo the 3d mono/stereo tm system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial signal for stereo inputs. srs dialog clarity the dialog clarity tm system is used to enhance dialog perception. srs trubass the srs ? trubass tm audio enhancement technology provides deep, rich bass to small speaker systems without the need for a subwoofer or additional extra physical components. for systems with a subwoofer, srs ? trubass tm complements and enhances bass performance. psycho-acoustically, when the human ear is presented with a low frequency sound signal that is missing the fundamental harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present. by accentuating the second and higher frequency harmonics of the bass portion of a signal, srs ? trubass tm gives the perception of greatly improved bass response. srs ? trubass tm is implemented on the loudspeakers path, the headphone path or on both paths in parallel. 2.8 svc (smart volume control) svc (smart volume control) regulates the audio signal level before audio processing. this regulation is necessary in order for the signal level to be independent from the source (terrestrial channels, i 2 s or scart), its modulation (fm) and annoying volume changes (for example, advertising). svc works as an audio compressor/expander; that is, when the input signal exceeds the threshold level, a very rapid attenuation (-2 db/ms) is applied to rescale the signal down to the threshold value. when the input signal is below the threshold level, the previous attenuation is reduced slowly in order to retrieve the original input level (0db gain). if the input signal is too low, an addition gain of 6 db can be provided. to personalize the action of the svc, five parameters are available: 1. threshold: maximum quasi-peak level that can be expected on output 2. peak measurement mode: selects the channel on which the peak measurement must be performed (left, right, center...) 3. release time: applies gain slope to the amplification phase 4. expander switch: allows a +6db amplification of small signals in order to reduce the output dynamic range 5. make up gain: allows compensation of the signal amplitude limitation by a 0 to 24 db adjustable gain. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 19/167 the svc is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). also, the svc can be applied in six-channel mode (l, r, l s , r s , c and subw). 2.9 st dynamic bass stv82x8 offers dynamic bass boost processing on the loudspeakers path. st dynamic bass tm is a bass boost process that can dramatically increase the bass content of any program without any output level saturation. three cutoff frequencies (bass_freq) can be chosen, 100 hz, 150 hz and 200 hz to adapt the effect to your loudspeakers. the amount of bass (bass_level) can also be fine tuned in order to adapt the effect loudness. 2.10 5-band audio equalizer the loudspeakers audio spectrum is split into five frequency bands and the gain of each of band can be adjusted within a range from -12 db to +12 db in steps of 0.25 db. the audio equalizer can be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. the equalizer is enabled by the ls_eq_on bit in the eq_bt_ctrl register. the gain value for band x is programmed in register ls_eq_bandx . the 5-band audio equalizer is exclusive with bas s-treble control. bit ls_eq_bt_sw in register eq_bt_ctrl is used to select either the 5-band audio equalizer or the bass-treble control for the loudspeakers path. depending on the ls equalizer or ls bass-treble value, the volume level can be clamped to the ls output to prevent any possible signal clipping by using the anticlip_ls_vol_clamp bit in the volume_modes (d7h) register. figure 12. equalizer 2.10.1 bass/treble control the gain of bass and treble frequency bands for the headphones can be also tuned within a range from -12 db to +12 db in steps of 0.25 db. it can be used to pre-define frequency band enhancement features dedicated to various kinds of music. the headphone bass/treble feature is enabled by setting the hp_bt_on bit in the eq_bt_ctrl register. the bass and treble gain values are adjusted in registers hp_bass_gain and hp_treble_gain , respectively. f 1 =100hz f 2 =330hz f 3 =1khz f 4 =3.3khz f 5 =6.6khz f 1 = 100 hz, f 2 = 330 hz, f 3 = 1 khz, f 4 = 3.3 khz and f 5 = 10 khz www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 20/167 depending on the hp bass-treble value, the volume level can be clamped to the hp output to prevent any possible signal clipping by us ing the anticlip_hp_vol_clamp bit in the volume_modes (d7h) register. 2.10.2 automatic loudness control as the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the loudness control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. while maintaining the amplitude of the 1 khz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 db when the audio volume level decreases.the maximum treble amplification can be adjusted from 0 db (first order loudness) to +18 db (second order loudness) in steps of 0.125 db. as the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. the loudspeakers loudness function is enabled by setting the ls_loud_on bit in register ls_loudness . the loudspeakers loudness threshold and maximum treble gain values are also programmed in this register. the headphone loudness function is enabled by setting the hp_loud_on bit in register hp_loudness . the headphone loudness threshold and maximum treble gain values are also programmed in this register. the loudness cut-off frequency is 100 hz. 2.11 volume/balance control the stv82x8 provides a volume/balance control for all output channels configurations (except s/pdif) with a different volume level per channel (l, r, c, l s , r s , subw, scart). its wide range (from +11.875 to -116 db, in a db linear scale with a 0.125 db step) largely covers typical home applications (approx. 60 db) while maintaining a good s/n ratio. figure 13. volume control an extra master volume control can apply an extra gain/attenuation on l, r, c, l s , r s and subw channels. output gain +11.875 db -116 db mute 00h 3ffh www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital signal processor 21/167 the volume/balance control can operate in one of two different modes: differential mode (default value): the volume control is a common volume value for both the left and right loudspeakers or headphone channels (see figure 13 ) and complimentary balance control is used (see figure 14 ). independent mode: the volume for the left and right channels for loudspeakers or headphones is controlled independently. figure 14. differential balance note: each step is 0.25db 2.12 soft mute control digital soft mute is applied smoothly (20 ms for 120 db range) to avoid any switch noise on the output. it is available on all output channels pairs: s/pdif channel (left/right) scart channels (left/right) loudspeakers channels (left/right) center subwoofer headphone/surround channels (left/right) another soft mute (analog) is also available on each dac output. 2.13 beeper the beeper is used to generate a tone on the loudspeakers or/and headphone outputs. the beeper sound (square wave) is added to the audio signal which is attenuated by 20 db. the beep sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and stopping. it can be used for various applications such as beep sounds for remote control, alarm clock or other features. output gain 100% mute 200h 1ffh i2c control (10 bits) 000h r i ght channel left channel www.datasheet.co.kr datasheet pdf - http://www..net/
digital signal processor stv82x8 22/167 the beeper operates in one of two modes: pulse mode (beep applications): a tone with a programmable short duration (0.1, 0.25, 0.5 and 1.0 s) is generated. afterwards, the beeper is automatically disabled and the output is switched back to the audio signal, see figure 15 . continuous mode (alarm application): a tone with a programmable long duration is generated. its start and stop controls must be programmed by i2c, see figure 16 . the beeper function is enabled by setti ng the beeper_on bit in register beeper_on . beeper parameters are controlled in register beeper_mode . the beeper tone level and frequency are programmed in register beeper_freq_vol . the level (or volume) ranges between 0 db and -93 db in steps of 3 db and the tone frequency ranges between 62.2 hz and 8 khz in steps of 1 octave. a beep generator is shared only by the loudspeakers or headphone outputs. therefore, in the event of simultaneous beeps when in pulse mode, only the first beep will define the effective duration that will be the same for both outputs. figure 15. pulse mode figure 16. continuous mode 2.14 internal audio/video delay (lip sync) internal audio/video delay is separately adjusted for loudspeakers and headphones by registers av_delay_time_ls (address eah) and av_delay_time_hp (address afh). using the delay: 117ms is the maximum available value. this delay applies to a stereo signal and can be fully used for loudspeaker or headphone outputs or shared between the two. in the 62.5 hz < f < 8 khz beep_on = 1 beep_on = 0 t predefined 0.1, 0.25, 0.5 and 1.0 s 62.5 hz < f < 8 khz beep_on = 1 beep_on = 0 t defined by i2c write www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 analog audio matrix (input/output) 23/167 latter case the total delay must not exceed 117ms and the priority is given to the loudspeakers. in the case of a 2.0 or 2.1 platform, even if the dpl or dplii decoder is used, the full delay is available. for a 5.1 platform, when dpl or dplii is used, one part of the delay is used for center and left and right surround channels and only a 66ms maximum delay can be used or shared for the loudspeaker or headphone outputs, or both. 2.15 scartaux channel the scartaux channel is available in the back end of audio processing, see figure 4 . this gives the possibility of an output in digital format (i2s) or analog format (using c/sub dac or srnd/hp dac selection is done by register headphone_config ) of a signal with the level of processing chosen by the cm_position_scartaux[1:0] bits. the analog outputs through c/sub dac or srnd/hp dac is 1v rms max amplitude signal. 3 analog audio matr ix (input/output) the analog part of the audio matrix can be divided into two parts: the scart input matrix and the scart output matrix. figure 17. scart input matrix the scart input matrix is an input for the digital matrix (after the adc) that selects which source is sent to the dsp. figure 18. scart 1/2/3 output matrix s2in s3in mono_in 2 audio adc select digital matrix s4in s5in* *tqfp100 package only s1in s2in s3in stereo dac 2 s1out select or mute s4in mono_in soft mute s5in* *tqfp100 only www.datasheet.co.kr datasheet pdf - http://www..net/
analog audio matrix (input/output) stv82x8 24/167 the scart 1 output matrix selects the sound to output, which can be directly a scart input or the output of the dsp. a mute function is provided to switch off the outputs. a soft-mute function is provided to avoid all spurious sounds when switching from one position to another position. the scart 2 and 3 output matrixes have the same functions as the scart 1 output matrix. the purpose of the matrix is to accept an input signal of 2 v rms and have the capability to output such a level. in this case, the power supply must be 8 v. the mono audio input is able to accept signals with a maximum 0.5 v rms amplitude. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 i2s interface (input/output) 25/167 4 i2s interface (input/output) 4.1 i2s inputs 4.1.1 i2s inputs in tqfp 80 package the stv82x8 can interface with a digital sound decoder. in this case, the digital data can be input at a speed of 0.384 mbytes/s (3.072 mhz for a 48 khz sampling frequency with 32 bits of data). a sample rate conversion (src) is necessary if the input frequency is not 48 khz (stv82x8 slave) in order to obtain a fixed frequency output from this block (48 khz). note: the src function is available only in single i2s input mode. the interface with one i2s connection (i2s_data0) enables the input of stereo or stereo- coded dolby ? pro logic ? . one interface with three i2s connections connected to the dsp enables the processing of a multi-channel signal (maximum of 6 channels). figure 19. tqfp 80 i2s input block diagram note: 1 the i 2s input and output modes are exclusive (this means that the i2s_data0 can be used as input or as output). 2 simultaneous processing of i2s inputs and si f inputs and adc inputs (scart or mono inputs) is possible with the device. 3 i2s_pcm_clk is not needed for the device. audio processing i2s_data0 i2s_data1 i2s_data2 fs input = 32 to 48 khz fs input = 48 khz only fs input = 48 khz only i2s_sclk i2s_lr_clk fs input = 32 to 48 khz fs input * 64 48 khz dsp processing www.datasheet.co.kr datasheet pdf - http://www..net/
i2s interface (input/output) stv82x8 26/167 4.1.2 i2s inputs in tqfp 100 package an i2sd_data input for external delay is available, but it must be in phase with the i2s output clocks. figure 20. tqfp100 i2s input block diagram note: 1 the i2s inputs can be used together with i2s outputs using i2so_data0 and i2so_data1. 2 simultaneous processing of i2s inputs and si f inputs and adc inputs (scart or mono inputs) is possible with the device. 3 i2s_pcm_clk is not needed for the device. audio processing i2s_data0 i2s_data1 i2s_data2 fs input = 32 to 48 khz fs input = 48 khz only fs input = 48 khz only i2s_sclk i2s_lr_clk fs input = 32 to 48 khz fs input * 64 48 khz dsp processing i2sd_data fs input = 48 khz in phase with i2so_lr_clk and i2so_sclk www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 i2s interface (input/output) 27/167 4.2 i2s outputs figure 21. i2s output selection 4.2.1 i2s outputs in tqfp 80 package a digital stereo output (i2s compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. in this case, the i2s_data0 signal and all clock signals are set as outputs by setting bit d5 in register reset to 1 (and bit d6 for the clocking). the stv82x8 drives the serial bus (i2s_sclk, i2s_lr_clk, and i22s_data0) in master mode in 64.fs format with a sampling frequency (f s ) of 48 khz. the i2s_pcm_clk signal can be used as a master clock for the slave interface, if required (frequency of pcm_clk is 256 x f s ). both standard and non-standard modes are available. figure 22. tqfp 80 i2s output block diagram spdif i2s out delay l/r dac c/sub dac srnd/hp dac scart dac i2so_data0 i2s_data0 i2so_data1 reg 59h bits [2:0] reg 59h bits [6:4] reg 56h bits [7:5] audio processing i2s_data0 fs output = 48 khz i2s_sclk i2s_lr_clk fs output = 48 khz fs output * 64 48 khz dsp processing i2s_pcm_clk fs output * 256 www.datasheet.co.kr datasheet pdf - http://www..net/
i2s interface (input/output) stv82x8 28/167 note: the i2s input and output modes are exclusive (this means that the i2s_data0 can be used as input or output). 4.2.2 i2s outputs in tqfp 100 package two digital stereo outputs (i2s compatible) ar e available for routing the demodulated signal or a converted input audio signal to an external device or perform an external delay. in this case, the i2so_data0 and i2so_data1 signals are available with all i2s inputs active. the control is done by register i2so_data_ctrl . the stv82x8 drives the serial bus (i2so_sclk,i2so_lr_clk, i2so_data0, and i2so_data1) in master mode in 64.fs format with a sampling frequency (fs) of 48 khz. the i2s_pcm_clk signal can be used as a master clock if required for the slave interface (frequency of pcm_clk is 256 x f s ). both standard and non-standard modes are available. figure 23. tqfp100 i2s output block diagram note: 1 the i2s inputs can be used together with i2s outputs using i2so_data0 and i2so_data1. audio processing i2so_data0 fs output = 48 khz i2so_sclk i2so_lr_clk fs output = 48 khz fs output * 64 48 khz dsp processing i2so_data1 fs output = 48 khz i2s_pcm_clk fs output * 256 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 i2s interface (input/output) 29/167 figure 24. i2s data format: lch = low, rch = high i2s_sclk 12 323 24 22 msb lsb 1 2 3 23 24 22 msb lsb 1 2 12 323 24 22 msb lsb 1 2 3 23 24 22 msb lsb 1 2 3 1/fs lch rch i2s_lr_clk (= 64fs) i2s_datax (standard mode) i2s_datax (non-standard mode) www.datasheet.co.kr datasheet pdf - http://www..net/
s/pdif input/output stv82x8 30/167 5 s/pdif input/output an s/pdif output is available for connection with an external a/v decoder/amplifier. the signal on this s/pdif output is selected by an on chip multiplexer between the internal signal and an external signal present on s/pdif bypass input (pin 44 for a tqfp80 package or pin 59 for a tqfp100 package) with spdif_mux bit in the dac_control register. the outputted internal signal can be selected from: l/r c/subwoofer hp or surround l/r scart l/r the external signal is for example the signal provided by an external dolby ? digital decoder (std2000). mute facility is also provided on the s/pdif output. note: the s/pdif_in pin (pin 44 for a tqfp80 package or pin 59 for a tqfp100 package) is a cmos digital pin and input signal on this pin must fulfill the characteristics as mentioned in section 17.12: digital i/os characteristics (0.5v pp standard s/pdif input level is not directly supported by the device and needs external circuitry). www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 power supply management 31/167 6 power supply management a mixed supply voltage environment requires the following voltages: 3.3v capable inputs/outputs for digital pins; 1.8v digital core; 8v capable inputs/outputs for analog audio interfaces (capability to output 2 v rms for scart requirements); 3.3v for stereo adc and dac (analog part); 1.8v for stereo adc and dac (digital part); 1.8v for if adc and agc. these voltages will be delivered by the application with an accuracy of 5% . for more information, refer to section 17.3: power supply data . other specific dc voltages or features are provided: voltage reference and biasing generation (agc, adcs, dacs), bandgap reference. 6.1 standby mode (loop-through mode) the stv82x8 provides a loop-through mode confi guration that bypasses ic functions via a scart i/o pin (full analog path only). in this case, only a minimum power of 200 mw is required. in standby mode, the digital and analog power supplies are switched off, except for pins vcc_h, vcc33_ls, vcc33_sc, and vcc_niso which are used to maintain the scart path with the last configuration programmed by analog matrixing (register scart1_2_output_ctrl and scart3_output_ctrl ). when switching back to normal full power mode, all i2c registers are reset except for those used in standby mode to maintain the original configuration. in standby mode, the i2c bus does not operate. however, the bus can still be used by other ics since the i2c i/o pins (sda and scl) of the stv82x8 are forced into a high-impedance configuration. 6.2 power on reset the following supply voltages are involved for power on reset for the stv82x8: tqfp80 1.8v: vdd18 on pins 38, 42, 50 and 66, vcc18_clk1 on pin 54 and vcc18_clk2 on pin 57. 3.3v: vdd33_ioi on pin 46 and vdd33_io2 on pin 59. tqfp100 1.8v: vdd18 on pins 50, 65 and 85, vcc 18_clk1 on pin 69 and vcc18_clk2 on pin 72. 3.3v: vdd33_ioi on pin 61 and vdd33_io2 on pin 74. www.datasheet.co.kr datasheet pdf - http://www..net/
power supply management stv82x8 32/167 the first condition for a valid reset is that all 1.8v supply voltages involved have reached a minimum valid voltage of 1.7v and that all 3.3v supply voltages involved have reached a minimum valid voltage of 3.1v. when this is the case and starting from this point, the reset must be maintained at a low level for at least 100 s then put to a high level. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 additional controls and flags 33/167 7 additional controls and flags this logic contains: headphone detection irq generation, the signal to be output to the mcu i2c bus expander output pin. 7.1 headphone detection for headphone, the hp_det input can be used to automatically mute the loudspeakers and subwoofer outputs when the hp_ls_mute bit is set in register headphone_config (active low). when a headphone is detected (the hp_det pin is set to 0) and the mute function is enabled. each change on the hp_det pin generates an irq request to the microprocessor on the irq pin. 7.2 irq generation four irqs are generated by the stv82x8. on each irq generation, the irq pin is set to 1. the pending irq status must be read at the i2s address 81h and the acknowledge is done by writing 0 to this register. the four available irqs are: irq0 : the identified tv sound standard is displayed in register autostd_status . each change in the detected standard is flagged to the host system via hardware pin irq. the flag must be reset by re-programming the irq bit in register autostd_ctrl and then checking the detected standard st atus by reading registers autostd_dem_status and autostd_time . irq1 : this irq is enabled only in digital input mode. in case of i2s synchronization loss, this irq is set to 1. irq2 : this irq is set to 1 when the device detects any change on the hp detection pin (headphone connection or de-connection). irq3 : on the stv82x8, same pins are used for both headphone and surround loudspeaker signal output. a change in the headphone configuration (hp active or not active) leads to a signal switch on those hardware pins. in or der to ensure a smooth audio transition, the output is soft muted before the signal is switched. the irq3 is then set to 1 to advise the master processor that the signal has been switched and to request an hp/srnd ouput un- mute. 7.3 i2c bus expander pin bus_exp can be used to control external switchable if saw filters or audio switches. this pin can be directly programmed by register reset . www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 reset stv82x8 34/167 8 stv82x8 reset all stv82x8 features are controlled via the i2c bus. the stv82x8 can be reset in 2 ways: by software via the i2c bus: this clears all synchronous logic, except for the i2c bus registers. by hardware via the reset pin: in additi on to clearing all synchronous logic, the reset input (active on the low level) re sets all the i2c bus registers to the default values listed below. table 2. reset default values function default mode demodulation auto-standard off scanned standards m/n btsc audio outputs automatic mute mode on loudspeaker source demodulated sound loudspeaker volume -40 db, differential mode, muted loudspeaker l/r balance l/r = 100% subwoofer -40 db / off headphone source demodulated sound headphone automatic detection on headphone volume -40 db, differential mode, muted headphone l/r balance l/r = 100% scart1 output demodulated sound scart2 output scart1 source scart3 output scart2 source i2s output (tqfp 100) mute www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 i2c interface 35/167 9 i2c interface 9.1 i2c address and protocol the stv82x8 i2c interface works in slave mode and is fully compliant with i2c standards in fast mode (maximum frequency of 400 khz). two pairs of i2c chip addresses are used to connect two stv82x8 chips to the same i2c serial bus. the device address pairs are defined by the polarity of the adr_sel pin and are listed in the following table: protocol description write protocol read protocol w = write address r = read address a = acknowledge n = no acknowledgement sub-address is the register address pointer; this value auto-increments for both write and read. note: a minimum of 1ms is necessary for a i2c write command to be taken into account. 9.2 start-up and configuration change procedure the dsp running loop is: read ic registers and update internal structures (memory variable) process sound samples write i2c registers with new updated values the step ?process sound sample? duration is 1ms . this is shown in figure 25 . table 3. i2c read/write addresses adr write address (w) read address (r) low (connected to gnd1) 80h 81h high (connected to vdd1) 84h 85h start w a sub-address a data a .... a data a stop start w a sub-address a stop start r a data a .... a data n www.datasheet.co.kr datasheet pdf - http://www..net/
i2c interface stv82x8 36/167 figure 25. simplified dsp processing flow when programming the i2c read/write register with addresses between 80h and ffh this flow has to be taken into account. for example, if two different values are written in the same register in less than 2 ms, it is possible that the dsp does not see the first value. this is because the second value overwrites the first one during the ?dsp pr ocessing? phase, before dsp can read the registers again. in the same way, when waiting for a register value change, the software program must wait for a least 2 ms in order to allow sufficient time for the dsp to update the register values. host run load patch file dsp run in it_m e m status? start dsp processing read i2c registers update internal structures read sim ultaneously the 128 i2c registers 0 1 dsp processing update i2c registers dsp processing tim e = 1m s 80h 81h 82h 83h 84h ? ? feh ffh w rite sim ultaneously the 128 i2c registers i2c registers (hw space) www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 i2c interface 37/167 figure 26. register update time duration of init phase < 1ms =0 (bit 0 in dsp_status register) device input configuration set-up (if needed) init_mem bit ? hardware reset pin low power on hardware reset pin high delay > 100 us software reset soft_rst = 1 delay > 5 ms delay > 5 ms (bit 0 in reset register address 01h) clock pll programmation load patch file see figure 36 =0 (bit 0 in dsp_status register) init_mem bit ? =1 host_run bit = 1 delay 2 ms initialization period (bit 0, dsp_run reg 85h) 82h = 03h check fw version software reset soft_rst = 0 (bit 0 in reset register address 01h) delay > 5 ms hw_reset = 1 is done by patch file at the end of patch loading. * * note: the customer can also set hw_reset = 1 here. (reg host_cmd = bit0, reg dsp_status address 84h) (init_mem = bit 0, reg dsp_status address 84h) if input configuration has to be changed, to be done here start dsp processing see figure 37 www.datasheet.co.kr datasheet pdf - http://www..net/
i2c interface stv82x8 38/167 9.3 process flow during patch loading and dsp initialization patch loading and dsp firmware initialization are shown in figure 27 figure 27. patch loading and dsp initialization dsp stop (hw_reset = 0) fw initialization patch loading write reg 6ah = 01h dsp start (hw_reset = 1) load patch in memory fw init phase write patch version (reg ffh = 06) fw initialization finished (init_mem = 1) sw launch patch loading patch file set hw_reset = 1 (done inside patch file) (reg host_cmd address 80h, bit 2) * * note: the customer can also set hw_reset = 1 here. (reg host_cmd address 80h, bit 2) duration of fw initialization is less than 1ms fw set init_mem = 1 (done inside patch file) (reg dsp_status address 84h, bit 0) sw must test init_mem = 1 before continue www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 i2c interface 39/167 9.4 input config uration change the input configuration change must be programmed as shown in figure 27 : figure 28. input configuration change set init_mem = 0 change input configuration unmute dacs dac mute & wait 50 ms for complete mute yes & ? restart dsw fw init_mem = 1 configuration change stop dsw fw & wait 5 ms no end www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 40/167 10 register list note: the unused bits (defined as ?reserved?) in the i2c registers must be kept to zero. the system clock registers (from address 08h to 0bh and from address 5ah to 5dh) do not need to be modified if a standard 27 mhz crystal oscillator is used. the default values of the demodulator register s (from address 0ch to 55h) are for optimum performances and any change is not recommended, except for: caroffset1 (22h) to compensate if carrier frequency with an out-of-standard offset. soundlevel prescaling prescale_demod_mono (94h), prescale_demod_stereo (95h), prescale_demod_sap (96h), prescale_scart (97h), prescale_i2s0 (98h), prescale_i2s1 (99h), prescale_i2s2 (9ah) to equalize demodulated or external audio signal before audio processing. peak detector registers peak_detector (9bh), peak_l (9ch), peak_r (9dh), peak_l_r (9eh) can be used to measure internal sound level. sound source selection for each audio output channel to be done using audio_matrix1 (a2h), audio_matrix2 (a3h) and audio_matrix3 (a4h). register autostd_ctrl (8ah) is used to select the list of mono, stereo and sap signals to be recognized automatically. note: () used in reset value column means that the bit or the byte is read-only. (s) symbol indicates that the field value is represented in signed binary format. 10.1 i2c register map by default, all i2c registers controlled by automatic standard recognition system (autostandard) are forced to read-only mode fo r the user. these registers and bits are shaded in ta bl e 4 . table 4. list of i2c registers name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ic general control cut_id 00h (0000 0001) 0 0 cut_number[5:0] reset 01h 0000 0000 bus_exp i2s_co_e n i2s_do_ en en_stby clock_ down 0 soft_ lrst1 soft_rs t i2s_ctrl 04h 0000 0001 i2s_pll sync_ sign i2s_src lock_th[1:0] lock_ mode sync_cst[1:0] i2s_stat 05h (0000 0000) 000000lr_off lock_ flag i2s_sync_offset 06h (0000 0000) i2s_sfo[7:0] clocking 1 sys_config 07h 0000 1010 sync_pl l open_pl l input_freq[3:0] bit[1:0] fs1_div 08h 0001 0011 en_pro g 0 ndiv1[1:0] 0 sdiv1[2:0] www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 41/167 fs1_md 09h 0001 0001 0 0 0 md1[4:0] fs1_pe_h 0ah 0011 0110 pe_h1[7:0] fs1_pe_l 0bh 0000 0000 pe_l1[7:0] demodulator demod_ctrl 0ch 0000 0001 0 0 0 0 0 demod_mode[2:0] demod_stat 0dh (0000 0000) 000000 fm1_ca r fm1_sq agc_ctrl 0eh 0001 0001 0 0 if_sele ct agc_ref[2:0] agc_cst[1:0] agc_gain 0fh (0000 0000) 0 agc_err[4:0] sig_ove r sig_ under dc_err_if 10h (0000 0000) dc_err[7:0] demodulator channel 1 carfq1h 12h 0010 1110 carfq1h[23:16] carfq1m 13h 1110 0000 carfq1m[15:8] carfq1l 14h 0000 0000 carfq1l[7:0] fir1c0 15h 0000 0001 fir1c0[7:0] (s) fir1c1 16h 0000 0000 fir1c1[7:0] (s) fir1c2 17h 1111 1110 fir1c2[7:0] (s) fir1c3 18h 1111 1100 fir1c3[7:0] (s) fir1c4 19h 0000 0000 fir1c4[7:0] (s) fir1c5 1ah 0000 1011 fir1c5[7:0] (s) fir1c6 1bh 0001 1001 fir1c6[7:0]6 (s) fir1c7 1ch 0010 0100 fir1c7[7:0] (s) acoeff1 1dh 0010 0010 acoeff1[7:0] bcoeff1 1eh 0000 1001 bcoeff1[7:0] crf1 1fh (0000 0000) crf1[7:0] (s) ceth1 20h 0010 0000 ceth1[7:0] sqth1 21h 0011 1100 sqth1[7:0] caroffset1 22h 0000 0000 caroffset1[7:0] (s) btsc stereo and sap stereo_conf 43h 00111000 lock_th_ste[3:0] loop_gain[1:0] freq_pi l reset stereo_fsm_con f 44h 00001110 0 0 bypass fsm_of f gain_ini[2:0] ste_de m stereo_level_h 45h 00100000 ste_lev_h[7:0] stereo_level_l 46h 00010000 ste_lev_l[7:0] sap_conf 47h 00000000 0 0 0 0 0 0 0 sap_sel sap_level_h 48h 00100000 sap_lev_h[7:0] sap_level_l 49h 00010000 sap_lev_l[7:0] table 4. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 42/167 10.2 software registers ste_car_lev 4ah (00000000) ste_car_lev[7:0] ste_pll_stat 4bh (00000000) 0 0 loop_gain[2:0] over lock_d et ste_det ste_sap_stat 4ch (00000000) 0 over lock_d et ste_det 0 0 sq_det sap_det pll_p_gain 4dh 01101100 pll_p_gain[7:0] pll_i_gain 4eh 0000011 0 0 0 0 pll_i_gain[3:0] sap_sq_th 4fh 00110000 sap_sq_th[7:0] analog and i 2 s out control i2s_adc_ctrl 56h 0000 1000 i2s_data0_ctrl 0 adc_ power_ up adc_input_sel[2:0] scart1_2_output _ctrl 57h 1010 1000 sc2_mu te sc2_output_sel[2:0] sc1_mu te sc1_output_sel[2:0] scart3_output_c trl 58h 0000 1011 0 0 0 0 sc3_mu te sc3_output_sel[2:0] i2so_data_ctrl 59h 0000 0000 0 i2so_data1_ctrl 0 i2so_data0_ctrl clocking 2 fs2_div 5ah 0001 0001 0 ndiv2[2:0] 0 sdiv2[2:0] fs2_md 5bh 0001 0001 0 0 0 md2[4:0] fs2_pe_h 5ch 0101 1100 pe_h2[7:0] fs2_pe_l 5dh 0010 1001 pe_l2[7:0] table 4. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 5. list of i2c registers name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dsp control host_cmd 80h 0000 0000 0 0 0 0 0 hw_res et 00 irq_status 81h 0000 0000 irq7 irq6 irq5 (hp/srnd unmute ready) irq4 (hp detected) irq3 (i2s src input freq change) irq2 (i2s sync found) irq1 (i2s sync lost) irq0 (autostan dard) fw_version 82h (0000 0001) soft_version[7:0] onchip_algos 83h (0000 0000) 00 prologi c_type multi_i2 s_in trubas s trusur round prolog ic multich annel_ out dsp_status 84h 0000 0000 0 0 0 0 0 0 0 init_me m dsp_run 85h 0000 0000 0 0 0 0 input_config registe rs_res et host_r un i2s_in_config 86h 1000 1110 lock_ mode_e n reset_i 2s 0 lrclk_s ta rt lrclk_p olarity sclk_p olarity data_cf g i2s_mod e www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 43/167 i2s_in_shift_right 87h 0000 1000 0 0 0 shift_right_range i2s_in_mask 88h 0001 1111 0 0 0 word_mask i2s_in_status 89h 1000 0(000) auto_sr c_sync enable_ irq_src _ freq_ change enable_ irq_syn c_foun d enable_ irq_syn c_lost 0 i2s_input_freq[2:0] automatic standard detection autostd_ctrl 8ah 0000 0000 single shot mono_ sap_mat rix_ctr l force_ sq_sap force_ sq_mon o auto_ mute sap_ check stereo _ check mono_ check autostd_time 8bh 0000 1010 0 0 0 stereo_time fm_time autostd_status 8ch (0000 0000) 0000 sap_ok stereo _ ok mono_o k autost d_on autostd_dem_stat us 8dh (0000 0000) 0 overfl ow lck_det st_det sap_sq sap_de t fm1_ca r fm1_sq i2s_in_delay_confi g 8fh 0000 0111 0 0 sync lrclk_ start lrclk_ polarit y sclk_ polarit y data_cf g i2s_mod e demodulator btsc_fine_prescal e_st 90h 0000 0000 btsc_fine_prescale_st[7:0] (s) btsc_fine_prescal e_sap 91h 0000 0000 btsc_fine_prescale_sap[7:0] (s) btsc_control 92h 0010 0000 fine_pr escal_s elect_s ap dbx_dematrix dbx_on deemphasis_ch1 deemphasis_ch0 dc_removal 93h 0011 0111 0 0 dbx_filt er_sele ct deemph asis_fil ter_sel ect 0 dc_dem od_pos t_on dc_dem od_pre _on dc_sca rt_on audio preprocessing and selection prescale_demod_ mono 94h 0000 0000 prescal e_demo d_selec t_sap prescale_demod_mono[6:0] (s) prescale_demod_ stereo 95h 0000 0000 0 prescale_demod_stereo[6:0] (s) prescale_demod_ sap 96h 0000 0000 0 prescale_demod_sap[6:0] (s) prescale_scart 97h 0000 0000 0 prescale_scart[6:0] (s) prescale_i2s0 98h 0000 0000 0 prescale_i2s0[6:0] (s) prescale_i2s1 99h 0000 0000 0 prescale_i2s1[6:0] (s) prescale_i2s2 9ah 0000 0000 0 prescale_i2s2[6:0] (s) peak_detector 9bh 0000 0000 0 peak_l_r_range[2:0] peak_det_input[2:0] peak_d etecto r_on peak_l 9ch 0(000 0000) overlo ad_l peak_l[6:0] table 5. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 44/167 peak_r 9dh 0(000 0000) overlo ad_r peak_r[6:0] peak_l_r 9eh 0(000 0000) overlo ad_l_r peak_l_r[6:0 matrixing downmix_mode 9fh 0111 1111 lt rt _ o u t_mode mix_out_mode[2:0] lfe_in mix_in_mode[2:0] downmix_dual_mo de a0h 0000 0000 0 0 0 dual_on ls_dual_select[1: 0] ltrt_dual_selec t [1:0] downmix_config a1h 0000 0001 0 0 srnd_factor[1:0] center_factor[1: 0] lr_upmi x normal ize audio_matrix1 a2h 0001 0010 0 0 hp_out[2:0] ls_out[2:0] audio_matrix2 a3h 0000 0010 0 0 scart2_out[2:0] scart1_out[2:0] audio_matrix3 a4h 0001 0000 0 0 spdif_out[2:0] delay_out[2:0] channel_matrix_l s a5h 0000 0010 autost d_cont rol_ls autost d_cont rol_spd if 0 0 0 cm_matrix_ls[2:0] channel_matrix_h p a6h 0000 0000 autost d_cont rol_hp cm_source_hp[1:0 ] cm_postion_hp[1:0 ] cm_matrix_hp[2:0] channel_matrix_s cart a7h 0000 0000 autost d_cont rol_sca rt cm_source_scar t[1:0] cm_postion_scar t[1:0] cm_matrix_scart[2:0] channel_matrix_s cartaux a8h 0000 0000 autost d_cont rol_sca rtaux cm_source_scar taux[1:0] cm_postion_scar ta u x [ 1 : 0 ] cm_matrix_scartaux[2:0] channel_matrix_s pdif a9h 0000 0000 cm_source_spdif[2:0] cm_postion_spdif [1:0] cm_matrix_spdif[2:0] demod_dc_level aah (0000 0000) demod_dc_level[7:0] (s) audio processing av_delay_config adh 0000 0000 0 0 0 0 0 0 dolby_ delay_ on av_dela y_on av_delay_time_ls aeh 0000 0000 av_delay_time_ls[7:0] av_delay_time_hp afh 0000 0000 av_delay_time_hp[7:0] pro_logic2_contr ol b0h 0111 0110 pl2_lfe pl2_output_downmix[2:0] pl2_modes[2:0] pl2_act ive pro_logic2_confi g b1h 0000 0000 0 0 0 pl2_srnd_filter[1: 0] pl2_rs_ polarit y pl2_pan orama pl2_aut obalan ce pro_logic2_dimen sion b2h 0000 0000 0 pl2_c_width[2:0] 0 pl2_dimension[2:0] pro_logic2_level b3h 0000 0011 pl2_level[7:0] noise_generator b4h 0000 0000 10_db_a ttenuat e sright_ noise sleft_ noise sub_ noise center _ noise right_ noise left_ noise noise_o n pcm_srnd_delay b5h 0000 0000 0 0 0 dolby_delay_srnd[4:0] table 5. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 45/167 pcm_center_delay b6h 0000 0000 0 0 0 0 dolby_delay_center[3:0] trusrnd_control b7h 0000 1000 dialog_ clarity _on headph one_on trusrnd_input_mode[3:0] trusrn d_bypas s trusrn d_on trusrnd_dc_eleva tion b8h 0000 1100 trusrnd_dc_elevation[7:0] trusrnd_input_gai n b9h 0000 0000 trusrnd_input_gain[7:0] trubass_ls_contr ol bah 0000 0110 0 0 0 0 trubass_ls_size[2:0] trubas s_ls_on trubass_ls_level bbh 00001 1001 trubass_ls_level[7:0] trubass_hp_cont rol bch 0000 0110 srs_tsx t_gain_ on 0 0 0 trubass_hp_size[2:0] trubas s_hp_o n trubass_hp_level bdh 0000 1001 trubass_hp_level[7:0] svc_ls_control beh 0000 0010 0 0 0 0 svc_ls_input[1:0] svc_ ls_amp svc_ ls_on svc_ls_time_th bfh 0000 0000 svc_ls_time[2:0] svc_ls_threshold[4:0] (s) svc_ls_gain c0h 0000 1111 0 0 svc_ls_make_up_gain[5:0] svc_hp_control c1h 0000 0010 0 0 0 0 0 0 svc_ lhp_am p svc_ hp_on svc_hp_time_th c2h 0000 0000 svc_hp_time[2:0] svc_hp_threshold[4:0] (s) svc_hp_gain c3h 0000 1111 0 0 svc_hp_make_up_gain[5:0] widesrnd_contro l c4h 0000 0100 0 0 0 0 0 widesr nd_ste reo widesr nd_mod e widesr nd_on widesrnd_freq c5h 0001 0101 0 0 widesrnd_bass[1: 0] widesrnd_mediu m[1:0] widesrnd_treble [1:0] widesrnd_level c6h 1000 0000 widesrnd_gain[7:0] omnisurround_co ntrol c7h 0000 1100 st_voice[1:0] srnd_p hase_in v omnisrnd_input_mode[3:0] omnisr nd_on dynamic_bass_ls c8h 0110 0010 ls_bass_level[4:0] ls_bass_freq[1:0] ls_dyn_ bass_o n dynamic_bass_hp c9h 0110 0010 hp_bass_level[4:0] hp_bass_freq[1:0 ] hp_dyn_ bass_o n eq_bt_ctrl cch 0000 0000 0 0 0 0 0 hp_bt_ on ls_eq_b t_sw ls_eq_ on ls_eq_bandx cdh 0000 0000 eq_band1[7:0] (s) ceh 0000 0000 eq_band2[7:0] (s) cfh 0000 0000 eq_band3[7:0] (s) d0h 0000 0000 eq_band4[7:0] (s) d1h 0000 0000 eq_band5[7:0] (s) ls_bass_gain d2h 0000 0000 ls_bass[7:0] (s) ls_treble_gain d3h 0000 0000 ls_treble[7:0] (s) table 5. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 46/167 hp_bass_gain d4h 0000 0000 hp_bass[7:0] (s) hp_treble_gain d5h 0000 0000 hp_treble[7:0] (s) output_bass_mng t d6h 1000 0000 bass_m anage_ on st_lfe_ add dolby_p rologic sub_ active gain_ switch ocfg_num[2:0] ls_loudness d7h 0000 0100 0 ls_loud_threshold[2:0] ls_loud_gain_hr[2:0] ls_ loud_o n hp_loudness d8h 0000 0100 0 hp_loud_threshold[2:0] hp_loud_gain_hr[2:0] hp_ loud_o n volume volume_modes d9h 1101 1111 antclip _hp_vol _clamp anticlip _ls_vol _clamp 0 scart2_ volume _ mode scart1_ volume _ mode hp_ volume _ mode srnd_ volume _ mode ls_ volume _ mode ls_l_volume_msb dah 1001 1000 ls_l_volume_msb[7:0] ls_l_volume_lsb dbh 0000 0000 0 0 0 0 0 0 ls_l_volume_lsb[ 1:0] ls_r_volume_msb dch 0000 0000 ls_r_volume_msb[7:0] ls_r_volume_lsb ddh 0000 0000 0 0 0 0 0 0 ls_r_volume_lsb [1:0] ls_c_volume_msb deh 1001 1000 ls_c_volume_msb[7:0] ls_c_volume_lsb dfh 0000 0000 0 0 0 0 0 0 ls_c_volume_lsb [1:0] ls_sub_volume_ms b e0h 1001 1000 ls_sub_volume_msb[7:0] ls_sub_volume_ls b e1h 0000 0000 0 0 0 0 0 0 ls_sub_volume_l sb[1:0] ls_sl_volume_msb e2h 1001 1000 ls_sl_volume_msb[7:0] ls_sl_volume_lsb e3h 0000 0000 0 0 0 0 0 0 ls_sl_volume_ls b[1:0] ls_sr_volume_msb e4h 0000 0000 ls_sr_volume_msb[7:0] ls_sr_volume_lsb e5h 0000 0000 0 0 0 0 0 0 ls_sr_volume_ls b[1:0] ls_master_volume _msb e6h 1110 1000 ls_master_volume_msb[7:0] ls_master_volume _lsb e7h 0000 0000 0 0 0 0 0 0 ls_master_volu me_lsb[1:0] hp_l_volume_msb e8h 1001 1000 hp_l_volume_msb[7:0] hp_l_volume_lsb e9h 0000 0000 0 0 0 0 0 0 hp_l_volume_lsb [1:0] hp_r_volume_msb eah 0000 0000 hp_r_volume_msb[7:0] hp_r_volume_ lsb ebh 0000 0000 0 0 0 0 0 0 hp_r_volume_lsb [1:0] aux_volume_in dex ech 0000 0001 0 0 0 0 0 0 aux_volume_sele ct [1:0] aux_l_volume_msb edh 1101 1101 aux_l_volume_msb[7:0] table 5. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 47/167 aux_l_volume_lsb eeh 0000 0000 0 0 0 0 0 0 aux_l_volume_ls b[1:0] aux_r_volume_ms b efh 0000 0000 aux_r_volume_msb[7:0] aux_r_volume_lsb f0h 0000 0000 0 0 0 0 0 0 aux_r_volume_ls b[1:0] mute mute_software f1h 1111 1111 hp d_mute spdif_d _mute scart2_ d_mute scart1_ d_mute srnd_d _mute sub_ d_mute c_ d_mute ls_ d_mute beeper beeper_on f2h 0000 0000 0 0 0 0 0 beeper_sound_s elect[1:0] beeper _ on beeper_mode f3h 0100 0011 beeper_decay[[2:0] beeper_duration[ 1:0] beeper _ contin uous beeper_path[1:0] beeper_freq_vol f4h 0111 0110 beeper_freq[2:0] beeper_volume[4:0] s/pdif out configuration spdif_out_channe l_status f5h 0000 0010 0 0 0 0 0 spdif_c opyrig ht spdif_n o_pcm spdif_c onsume r_pro headphone configuration headphone_confi g f6h 0000 0010 0 0 scartaux_out_sel ect hp_for ce hp_ls_ mute hp_det_ active hp_ detect ed dac control dac_control f7h 0001 1111 0 0 spdif_ mux dac_sca rt_mute dac_shp _mute dac_cs ub_mut e dac_lsl r_mute power_ up sw1_channels f8h 0000 0000 c_sub_sw[1:0] sur_hp_sw[1:0] scart_sw[1:0] spdif_sw[1:0] sw2_channels f9h 0000 0000 0 0 0 0 delay_sw[1:0] l_r_sw[1:0] autostandard coefficients settings autostd_coeff_ct rl fbh 0000 0001 0 0 0 0 0 0 autostd_coeff_ ctrl[1:0] autostd_coeff_in dex_msb fch 0000 0000 0 0 0 0 0 0 0 autost d_coef f_index _msb autostd_coeff_in dex_lsb fdh 0000 0000 autostd_coeff_index_lsb[7:0] autostd_coeff_va lue feh 0000 0000 autostd_coeff_value[7:0] patch_version ffh 0000 0000 patch_version[7:0] table 5. list of i2c registers (continued) name addr. reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 48/167 10.3 stv82x8 general control registers cut_id version identification address: 00h type: ro reset: 0000 0001 reset software reset address: 01h type: r/w reset: 0000 0000 description: the built-in automatic standard recognition system (autostandard) can be disabled. in this case, the software reset function (bits soft_lrst1 and soft_lrst2) can be used to implement the autostandard by i2c software. this is not required if the built-in autostandard function is used (default) . 7 6543210 0 0 cut_number[5:0] ro [7:6] reserved [5:0] dice version identification 76543210 bus_exp i2s_co_en i2s_do_en en_stby clock_down 0 soft_lrst1 soft_rst r/w [7] static control by i 2 c of hardware pin bus_exp [6] 0 = i2s input (i2s_sck, i2s_lr_clk, i2s_pcm_clk in input mode) 1 = i2s output (i2s_sck, i2s_lr_clk, i2s_pcm_clk in output mode) [5] 0 = i2s input (i2s_data0 in input mode) 1 = i2s output (i2s_data0 in output mode) [4] standby mode enabling: 0: normal mode 1: lock the digital signals before putting the device in standby mode [3] clock down of the dsp decoder. [2] reserved note: the following register bit is controlled by au tostandard and is forced by default to read-only mod e. [1] softreset (active high) of decoder. [0] general softreset (active high) to reset all hardware registers except for i22c data. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 49/167 i2s_ctrl i2s synchronization control address: 04h type: r/w reset: 0000 0001 i2s_stat i2s sync hronization status ) address: 05h type: r/w reset: 0000 0000 76543210 i2s_pll sync_sign i2s_src lock_th[1:0] lock_mode sync_cst[1:0] r/w [7] i2s source synchronization with syn thesizer (at 48khz only) activation: 0: selected 1: not selected [6] sign of the loop reversion (to be used in case of gain inversion of the frequency synthesizer) [5] src i2s source activation: 0: on 1: off [4:3] lock detector threshold programming: 00: 1 clk period error of accumulation 01: 2 clk period error of accumulation 10: 4 clk period error of accumulation 11: 8 clk period error of accumulation [2] lock detector mode: 0: lock when accumulation error within lock th reshold and lr detected (period counter not saturated 1: lock only when accumulation error within lock threshold. not interested in lr detection [1:0] synchronization time constant. defines the measurement period of lr: 00: half period measured (lowest accuracy) 01: one full period measured 10: two full periods measured 11: four full periods measured (highest accuracy) 76543210 000000lr_offlock_flag r/w [7:2] reserved [1] lr signal detection: 0: lr signal detected and correct 1: missing lr pulses detected www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 50/167 i2s_sync_offset i2s synchroni zation offset frequency address: 06h type: r/w reset: 0000 0000 10.4 clocking 1 a low-jitter pll clock is integrated and can be fully reprogrammed using the registers described below. by default, the programming is defined for a 27-mhz crystal oscillator, which is the frequency recommended for reducing potential rf interference in the application. however, if necessary, the pll clock can be re-programmed for other crystal oscillator frequencies within a range from 23 to 30 mhz. other crystal frequencies can be programmed on your demand. note: a crystal frequency change is compatible with other default i2c programming including the built-in automatic standard recognition system. sys_config system configuration control address: 07h type: r/w reset: 0000 1010 [0] lock flag allowing unmute of audio output 76543210 i2s_sfo[7:0] r/w [7:0] i2s synchronization frequency offset (450 ppm full scale) 76543210 sync_pll open_pll input_freq[3:0] bit[1:0] r/w [7] status of the loop with the synthesizer: 0: open 1: closed [6] force the loop with the synthesizer to be open: 0: no action 1: loop open [5:2] i 2 s input frequency: 0010: 48 khz [1:0] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 51/167 fs1_div fs1 i/o divider programming address: 08h type: r/w reset: 0001 0011 fs1_md fs1 coarse selection address: 09h type: r/w reset: 0001 0001 fs1_pe_h fs1 fine selection (msbs) address: 0ah type: r/w reset: 0011 0110 76543210 en_prog 0 ndiv1[1:0] 0 sdiv1[2:0] r/w [7] fs1 programming enable: 0: fs1 i 2 c register programming ignored by system - fs1 pre-programmed automatically by sys-config register (normal use wi th standard oscillator of 27 mhz) 1: fs1 i 2 c register programming used by system - fs1 pre-programming by sys-config deactivated (to be used in case of no standard oscillator, other than 27 mhz) [6] reserved [5:4] fs1 input clock divider selection [3] reserved [2:0] fs1 output clock divider selection 76543210 000 md1[4:0] r/w [7:5] reserved [4:0] fs1 coarse selection 76543210 pe_h1[7:0] r/w [7:0] fs1 fine selection (msbs) www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 52/167 fs1_pe_l fs1 fine selection (lsbs) address: 0bh type: r/w reset: 0000 0000 10.5 demodulator demod_ctrl demodulator control address: 0ch type: r/w reset: 0000 0001 demod_stat demodulator detection status address: 0dh type: ro reset: 0000 0000 7654 3 210 pe_l1[7:0] r/w [7:0] fs1 fine selection (lsbs) 76543210 00000 demod_mode[2:0] r/w [7:3] reserved note: this register is controlled by autost andard and is forced by def ault to read-only mode. [2:0] demodulator mode selection: demod fm 000: normal 001: wide other configuration: reserved 7654 3210 0 0 0 fm1_car fm1_sq ro [7:2] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 53/167 note: these registers allow direct acce ss to the demodulator signal detectors. agc_ctrl if agc control address: 0eh type: r/w reset: 0001 0001 [1] channel 1 fm carrier detector flag: 0: not detected 1: detected [0] channel 1 fm squelch selector flag: 0: not detected 1: detected 76543210 0 0 if_select agc_ref[2:0] agc_cst[1:0] r/w [7:6] reserved [5] selection of the if input:. 0: if input sif 1 1: if input sif 2 [4:2] defines the clipping level which adjusts the al lowable proportion of samples at the input of the adc which will be clipped. the agc tr ies to maximize the use of the full scale range of the adc. the default setting gives a ratio of 1/256. clipping ratio 000: 1/16 (single carrier) 001: 1/32 010: 1/64 011: 1/128 100: 1/256 (default) 101: 1/512 110: 1/1024 111: 1/2048 (multiple carriers) [1:0] agc time constant this is the time constant betw een each step of 1.5 db by the agc. step duration (ms) 00: 1.33 00: 1.33 01: 2.66 10: 5.33 11: 10.66 www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 54/167 agc_gain if agc control and status address: 0fh type: r/w reset: 0000 0000 dc_err_if dc offset status for if adc address: 10h type: ro reset: 0000 0000 10.6 demodulator channel 1 carfq1h channel 1 carrier dco frequency 76543210 0 agc_err[4:0] sig_over sig_under r/w [7] reserved [6:2] amplifier gain control. this is the agc gain control value. there are 20 steps of +1.5 db (see note below): 00000: gain-min 10100: gain-min + 30 db 11111: gain-min + 30 db [1] agc input signal upper threshold: 0: normal signal 1: signal too large and agc overloaded [0] agc input signal lower threshold: 0: normal signal 1: signal too small and agc is underloaded when the agc is in automatic mode (agc_c md = 0), bits sig_over and sig_under indicate if the input signal is too small/large and the agc is under/overloaded. this is useful when setting the stv82x8 sif input level. 7654321 0 dc_err[7:0] ro [7:0] dc offset error of if adc output 76543210 carfq1h[23:16] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 55/167 address: 12h type: r/w reset: 0010 1110 carfq1m channel carrier dco frequency address: 13h type: r/w reset: 1110 0000 carfq1l channel 1 carrier dco frequency address: 14h type: r/w reset: 0000 0000 note: carrier frequency: carfq1(dec).f s / 2 24 with f s = 24.576 mhz (crystal oscillator frequency independent) [7:0] channel 1 dco carrier frequency (8 msbs). note: this register is controlled by autost andard and is forced by default to read-only mode 76543210 carfq1m[15:8] r/w [7:0] channel 1 dco carrier frequency. note: this register is controlled by autost andard and is forced by default to read-only mode 76543210 carfq1l[7:0] r/w [7]:0 channel 1 dco carrier frequency (8 lsbs), see ta bl e 6 .. note: this register is controlled by autost andard and is forced by def ault to read-only mode. table 6. mono carrier frequencies by system system mono carrier frequency. (mhz) carfq1[23:0] (dec) carfq1[23:0] m/n 4.5 3072000 2ee000h www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 56/167 fir1c[0:7] channel 1 fir coefficients address: 15h type: r/w reset: 0000 0001 note: the above registers are controlled by autostandard and are forced by default to read-only mode. acoeff1 channel 1 baseband pll loop filter proportional coefficient address: 1dh type: r/w reset: 0010 0010 76543 210 fir1c0[7:0] to fir1c7[7:0] r/w bitfield description (reset state) fm 27 khz fm 50 khz fm 200 khz fm 350 khz fm 500 khz btsc fir1c0[7:0] ffh 00h 00h 02h 01h 01h fir1c1[7:0] feh feh 01h 01h 00h 00h fir1c2[7:0] feh fch 01h fch 04h feh fir1c3[7:0] 00h fdh fch 03h fah fch fir1c4[7:0] 06h 02h 08h 04h 05h 00h fir1c5[7:0] 0eh 0dh f6h f2h 00h 0bh fir1c6[7:0] 16h 18h f8h 06h f2h 19h fir1c7[7:0] 1bh 1fh 4ah 43h 4dh 24h 76543210 acoeff1[7:0 r/w [7]:0 used to program the proportional coeffici ent of the baseband pll loop filter (channel 1) defines the damping factor of the loop. for values, refer to ta b l e 7 . note: this register is controlled by autost andard and is forced by def ault to read-only mode. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 57/167 bcoeff1 channel 1 baseband pll loop filter integral coefficient & dco gain address: 1eh type: r/w reset: 0000 1001 ( * ) refer to demod_ctrl (demod_mode[2:0]) crf1 channel 1 baseband pll demodulator offset address: 1fh type: ro reset: 0000 0000 76543210 bcoeff1[7:0] r/w [7]:0 used to program the integral coefficient of the baseband pll loop filter and dco gain. defines the bandwidth of the loop. for values, refer to ta bl e 7 . note: this register is controlled by autost andard and is forced by default to read-only mode table 7. baseband pll loop filter adjustment (fm mode) fm mode small standard medium wide* btsc acoeff 10h 22h 2ch 2ch 22h bcoeff 1ah 12h 0ah 0ah 09h fm_dev max (khz) 62.5 125 250 500 500 dco range (khz) 96 192 384 768 768 76543210 crf1[7:0] ro [7:0] channel 1 carrier recovery frequency. displays the instantaneous frequency offset of the channel 1 baseband pll demodulator. www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 58/167 ceth1 channel 1 fm carrier level threshold address: 20h type: r/w reset: 0010 0000 sqth1 channel 1 fm squelch threshold address: 21h type: r/w reset: 0011 1100 76543210 ceth1[7:0] r/w [7:0] this register is used to compare the carrier level in the channel and the threshold value. this level is measured after the channel filter and is re lative to the full scale reference level (0 db). this is used as part of the validation of an fm signal, if the carrier level is below the threshold, the signal is considered to be non-valid. recommended value is 10h. ceth threshold (db) ffh -6 80h -12 40h -18 20h -24 (default) 10h -32 (recommended value) 08h -38 off (all carrier levels are accepted) 76543210 sqth1[7:0] r/w [7:0] the squelch detector measures the level of high frequency noise and compares it to the threshold level (sqth). if the level is below this value, the s/n of the fm signal is considered to be acceptable. values are given for fm with standard deviation. sqth s/n (db) fa h0 77 h10 3c h15 (default) 23 h20 19 h25 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 59/167 caroffset1 channel 1 dco carrier offset compensation address: 22h type: r/w reset: 0000 0000 stereo_conf btsc stereo configuration address: 43h type: r/w reset: 0011 1000 76543210 caroffset1[7:0] (s) r/w [7:0] this value is used to correct the carrier fr equency offset of the incoming if signal. automatic frequency control in fm mode can be implemented by registers dc_removal . a dco frequency offset (in two?s complement form at) is added to the pre- programming value by autotsd in the carfq1 registers (corresp onding to the standard if carrier frequency). the programmable carrier offset ranges from -192 kh z to +190.5 khz with a resolution of 1.5 khz. for standard fm deviation, the value displays by dc_removal can be directly loaded in caroffset1 to exactly compensate the carrier offset on channel 1 76543210 lock_th_ste[7:4] loop_gain[1:0] freq_pil reset r/w [7:4] btsc lock stereo threshold [3:2] gain of stereo pll: 00: gain * 4 01: gain * 2 10: gain (default) 11: g ain / 2 [1] pilot frequency selection: 0: 15.625-15.734 khz 1: reserved note: the following register bit is controlled by autostandard and is forced by default to read-only mode [0] stereo reset: 1: reset active. www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 60/167 stereo_fsm_conf btsc finite state machine configuration address: 44h type: r/w reset: 0000 1110 stereo_level_h btsc threshold high for stereo detection address: 45h type: r/w reset: 0010 0011 note: this parameter can only be modified when auto standard is off. stereo_level_l btsc threshold low for stereo detection address: 46h type: r/w reset: 0000 1100 76543 210 0 0 bypass fsm_off gain_ini[2:0] ste_dem r/w [7:6] reserved [5] bypass of the stereo block: 0: stereo block is on 1: stereo block is bypassed [4] fsm switch off: 0: fsm is on 1: fsm is off. gain set by i2c [3:1] initial loop gain for fsm [0] stereo dematrix inside the stereo block (before dbx): 1: reset active 76543210 ste_lev_h[7:0] r/w [7:0] threshold high for stereo detection. if carr ier level is > ste_lev_h, stereo is detected. 7654321 0 ste_lev_l[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 61/167 note: this parameter can only be modified when auto standard is off. sap_conf btsc sap selection address: 47h type: r/w reset: 0000 0000 sap_level_h btsc threshold high for sap detection address: 48h type: r/w reset: 0101 0000 note: this parameter can only be modified when auto standard is off. sap_level_l btsc threshol d low for sap detection address: 49h type: r/w reset: 0011 0000 [7:0] threshold low for stereo detection. if carrier level is sap_lev_h, sap is detected. 76543210 sap_lev_l[7:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 62/167 note: this parameter can only be modified when auto standard is off. ste_car_lev btsc stereo carrier level address: 4ah type: ro reset: 0000 0000 ste_pll_stat btsc stereo pll status address: 4bh type: ro reset: 0000 0000 [7:0] threshold low for sap detection. if sap signal level is stv82x8 register list 63/167 ste_sap_stat btsc stereo sap status address: 4ch type: ro reset: 0000 0000 pll_p_gain btsc pll proportional gain address: 4dh type: r/w reset: 0110 1100 76543210 0 over lock_det ste_det 0 0 sq_det sap_det ro [7] reserved [6] overflow append in stereo search process: 1: overflow [5] stereo pll lock status: 0: no lock on pilot 1: lock on pilot or no pilot detected (no stereo) [4] stereo detection: 0: no stereo detected 1: stereo detected [3:2] reserved [1] squelch detection of sap; 0: problem with noise 1: level of noise is good [0] signal detection of sap: 0: sap not detected 1: sap detected 76543210 pll_p_g[7:0] r/w [7:0] pll proportional gain www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 64/167 pll_i_gain btsc pll integral gain address: 4eh type: r/w reset: 0000 0011 sap_sq_th sap squelch threshold address: 4fh type: r/w reset: 0011 0000 10.7 i 2 s and analog control i2s_adc_ctrl i2s_data0 and adc input selection and power-up address: 56h type: r/w reset: 0000 1000 76543210 0 0 0 0 pll_i_g[3:0] r/w [7:4] reserved [3:0] pll integral gain 76543210 sap_sq_th[7:0] r/w [7:0] sap squelch threshold 76543210 i2s_data0_ctrl[2:0] 0 adc_ power_up adc_input_sel[2:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 65/167 scart1_2_output_ctrl scart 1_2 output selection and mute address: 57h type: r/w reset: 1010 1000 scart3_output_ctrl scart 3 output selection and mute address: 58h type: r/w reset: 0000 10111 76543210 sc2_mute sc2_output_sel[2:0] sc1_mute sc1_output_sel[2:0] r/w [7] mute command for the output scart 2: 0: output not muted 1: output muted [6:4] selection of the output scart 2 configuration: 000: dsp 001: input mono 010: input scart 1 (def) (b sdip 64) 011: input scart 2 (res. sdip 64) 100: input scart 3 (res. sdip 64) 101: input scart 4 (res. sdip 64) 110: input scart (res. tqfp) (a sdip 64) (1_bis) 111: input scart (5 tqfp 100) (c sdip 64) (3_bis) [3] mute command for the output scart 1: 0: output not muted 1: output muted [2:0] selection of the output scart 1 configuration: 000: dsp (default) 001: input mono 010: input scart 1 (b sdip 64) 011: input scart 2 (res sdip 64) 100: input scart 3 (res. sdip 64) 101: input scart 4 (res. sdip 64 110: input scart (res. tqfp) (a sdip 64) (1_bis) 111: input scart (5 tqfp100) (c sdip64) (3_bis) 765432 0 0 0 0 0 sc3_mute sc3_output_sel[2:0] r/w [7:4] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 66/167 i2so_data_ctrl i 2 s data source control l address: 59h type: r/w reset: 0000 0000 [3] mute command for the output scart 3: 0: output not muted 1: output muted [2:0] selection of the output scart 3 configuration: 000: dsp 001: input mono 010: input scart 1 (b sdip) 011: input scart 2 (default) 100: input scart 3 (res. sdip 64) 101: input scart 4 (res. sdip 64) 110: input scart (res. tqfp) (a sdip64) (1_bis) 111: input scart (5 tqfp 100) (c sdip 64) (res. sdip 64) (3_bis) 76543210 0 i2so_data1_ctrl[2:0] 0 i2so_data0_ctrl[2:0] r/w [7] reserved [6:4] source selection for i2so_data1 output: 000: mute 001: lr 010: hp_lss 011: ls_c and ls_sub 100: scart dac 101: s/pdif_out 110: delay 111: mute [3] reserved [2:0] source selection for i2so_data0 output: 000: mute 001: lr 010: hp_lss 011: ls_c and ls_sub 100: scart dac 101: s/pdif_out 110: delay 111: mute www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 67/167 10.8 clocking 2 fs2_div fs2 i/o divider programming address: 5ah type: r/w reset: 0010 0001 fs2_md fs2 coarse selection address: 5bh type: r/w reset: 0001 0001 fs2_pe_h fs2 fine selection (msbs) address: 5ch type: r/w reset: 0101 1100 76543210 0 0 ndiv2[1:0] 0 sdiv2[2:0] [7:6] reserved [5:4] fs2 input clock divider selection [3] reserved [2:0] fs2 output clock divider selection 7654321 0 0 0 0 md2[4:0] r/w [7:5] reserved [4:0] fs2 coarse selection 76543210 pe_h2[7:0] r/w [7:0] fs2 fine selection (msbs) www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 68/167 fs2_pe_l fs2 fine selection (lsbs) address: 5dh type: r/w reset: 0010 1001 10.9 dsp control host_cmd dsp hardware control address: 80h type: r/w reset: 0000 0000 irq_status irq status address: 81h type: r/w reset: 0000 0000 76543210 pe_l2[7:0] r/w [7:0] fs2 fine selection (lsbs) 76543210 0 0 0 0 0 hw_reset 0 0 r/w [7:3] reserved [2] dsp hardware run when set, see figure 26 . [1:0] reserved 76543210 irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 r/w [7:6] reserved [5] hp/srnd dac unmute ready irq [4] hp detected irq [3] i 2 s src frequency change detected irq [2] i 2 s sync found irq www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 69/167 fw_version embedded firmware version address: 82h type: ro reset: 0000 0001 onchip_algos display algorithms available on the chip address: 83h type: ro reset: 0000 0000 [1] i 2 s sync lost irq [0] autostandard irq 76543210 fw_version[7:0] ro [7:0] version of the embedded software. 76543210 00 prologic_ty pe multi_i2s_in trubass tru surround prologic multichannel _out ro [7:6] reserved [5] 0: pro logic 1 1: pro logic 2 [4] 0: 1 i 2 s input 1: 3 i 2 s inputs [3] srs trubass algorithm is present when set. [2] srs trusurround algorithm is present when set. [1] dolby pro logic algorithm is present when set. [0] multi-channel output is present when set. www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 70/167 dsp_status dsp status address: 84h type: ro reset: 0000 0000 dsp_run dsp configuration and run address: 85h type: r/w reset: 0000 0000 i2s_in_config i 2 s configuration address: 86h type: r/w reset: 1000 0111 76543210 0000000init_mem ro [7:1] reserved [0] dsp initialization: 0: dsp is not initialized 1: dsp is initialized 76543210 0000 input_config registers_r eset host_run r/w [7:4] reserved [3:2] 00: btsc + i2s src + i2s delay + adc 01: btsc + i2s 48k + i2s delay + adc 10: not used 11: btsc + multi i2s 48k + adc [1] 0: 2c register table is no t initialized when soft reset 1: 2c register table is initialized when soft reset [0] 0: soft reset dsp 1: start dsp processing 76543210 lock_mode_e n reset_i2s sync lrclk_start lrclk_pola rity sclk_pola rity data_cfg i2s_mode r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 71/167 note: this register must be set before the start of the software (85h: host_run = 1). i2s_in_shift_right i 2 s shift right address: 87h type: r/w reset: 0000 1000 note: this register has to be set before starting the software (0x85 : host_run = 1). i2s_in_mask i 2 s mask address: 88h type: r/w reset: 0001 1111 [7] enable lock mode for external i 2 s input: 0: disable lock mode for external i 2 s input 1: enable lock mode for external i 2 s input [6] reset i 2 s input sync when set [5] i 2 s synchronization: 0: direct capture 1: wait for sync signal [4] according to lrclk polarity, first data take: 0: left 1: right [3] polarity of the left data [2] 0: falling edge 1: rising edge [1] 0: lsb first 1: msb first [0] 0: not standard mode 1: standard mode 7654321 0 0 0 shift_right_range[4:0] r/w [7:5] reserved [4:0] defines the shift right to apply to 32-bit input samples. range: 0 to 31 76543210 0 0 0 word_mask[4:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 72/167 note: this register has to be set before starting the software (0x85 : host_run = 1). i2s_in_status src i 2 s input behavior address: 89h type: r/w reset: 1000 0000 [7:5] reserved [4:0] defines the mask to apply to 32-bit input samples. range: 0 to 31 76543210 auto_src_sy nc enable_irq_s rc_freq_cha nge enable_irq_s ync_found enable_irq_s ync_lost 0 i2s_input_freq r/w [7] allow the dsp to reset the src input dma w hen an input freq change is detected. (working in src mode only): 0: no reset on input frequency change 1: reset on input frequency change [6] generate an irq3 when a frequency change is de tected on src input. (working in src mode only): 0: rq3 generation not active 1: rq3 generation active [5] generate an irq2 when a signal is synchroniz ed on src input. (worki ng in src mode only): 0: rq2 generation not active 1: rq2 generation active [4] generate an irq1 when a signal is lost on src input. (working in src mode only): 0: rq1 generation not active 1: rq1 generation active [3] reserved [2:0] display the frequency detected on src input: 000: no signal locked on src input 001: 32 khz 010: 44.1 khz 011: 48 khz 100: signal locked but frequency unknown 101: not used 110: not used 111: not used www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 73/167 10.10 automatic standard recognition autostd_ctrl automatic standard recognition control l address: 8ah type: r/w reset: 0000 0000 76543210 single_shot mono_sap_ct rl_matrix force_sq_sa p force_sq_m ono auto_mute sap_check stereo_chec k mono_check r/w [7] single-shot mode (to be selected with any of the mono/stereo or sap check bits): 0: single shot mode is not selected 1: single shot mode is selected (1) [6] changes the behavior of the automatic matrix control for sap language: 0: when sap signal is detected, the sap si gnal is outputted on both left and right channels 1: when sap signal is detected, mono signal is outputted on the left channel and the sap signal is outputted on the right channel [5] force the squelch status during sap detection by autostandard. 0: sap squelch from demod status 1: sap squelch forced to 1 [4] force the squelch status duri ng mono detection by autostandard. 0: mono squelch from demod status 1: mono squelch forced to 1 [3] 0: output channels are never muted 1: output channels are automatically muted when no signal is detected [2] 0: no sap standard research 1: sap standard research [1] 0: no stereo standard research 1: stereo standard research (prior ity is given to sap if selected) [0] 0: no mono standard research (autostandard off) 1: mono standard research (m andatory to activate autostandard) 1. s ingle_shot mod e pre-programs demodulator registers in a chosen standard (bits b2, b1, b0). autostandard is switched off (mono_check = 0) after the programming of the registers. www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 74/167 autostd_time detection time-out address: 8bh type: r/w reset: 0000 1010 note: the time-out default value is optimum and does not normally need to be changed. autostd_status detection standard status address: 8ch type: ro reset: 0000 0000 76543210 0 0 0 stereo_time[2:0] fm_time[1:0] r/w [7:5] reserved [4:2] stereo detection time-out: 000: 20 ms (default) 001: 40 ms 010: 100 ms 011: 200 ms 100: 400 ms 101: 800 ms 110: 1200 ms 111: 1600 ms [1:0] fm detection time-out: 00: 16 ms 01: 32 ms 10: 48 ms (default) 11: 64 ms 76543210 0000 sap_ok stereo_ok mono_ok autostd_on ro [7:4] reserved note: the following register bits are controlled by autostandard and are forced by default to read-only mode [3] sap standard recognition status: 0: sap standard not detected 1: sap standard detected [2] stereo standard recognition status: 0: stereo standard not detected 1: stereo standard detected www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 75/167 autostd_dem_status demodulator status address: 8dh type: ro reset: 0000 0000 [1] mono standard recognition status: 0: mono standard not detected 1: mono standard detected [0] automatic standard recognition system status: 0: automatic standard recognition system is off 1: automatic standard recognition system is on 76543210 0 overflow lck_det st_det sap_sq sap_det fm1_car fm1_sq ro [7] reserved note: the following register bits are controlled by autostandard and are forced by default to read-only mode [6] overflow [5] lock detection: 0: stereo lock not detected 1: stereo lock detected [4] stereo lock detection: 0: stereo not detected 1: stereo detected [3] sap squelch detection: 0: sap squelch not detected 1: sap squelch detected [2] sap detection: 0: sap not detected 1: sap detected [1] fm1 carrier detection: 0: fm1 carrier not detected 1: fm1 carrier detected [0] fm1 squelch detection: 0: fm1squelch detected 1: fm1 squelch detected www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 76/167 i2s_in_delay_config i 2 s configuration for delay input address: 8fh type: r/w reset: 1000 1110 note: for this input, the shift_right and mask of the i 2 s input are set. shift_right = 0x08 mask = 0x1f 10.11 demodulator btsc_fine_prescale_st btsc input prescale for stereo mode address: 90h type: r/w reset: 0000 0000 7654321 0 0 0 sync lrclk_start lrclk_polari ty sclk_polarit y data_cfg i2s_mode r/w [7:6] reserved [5] i2s synchronization: 0: direct capture 1: wait for synchronization signal [4] according to lrclk polarity, first data take: 0: left 1: right [3] polarity of the left data [2] 0: falling edge 1: rising edge [1] 0: lsb first 1: msb first [0] 0: not standard mode 1: standard mode 76543210 btsc_fine_prescale_st[7:0] (s) r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 77/167 btsc_fine_prescale_sap btsc input prescale for sap mode address: 91h type: r/w reset: 0000 0000 btsc_control btsc back-end decoder control address: 92h type: ro reset: 0000 0000 [7:0] set the prescale of the signal coming from the demodulato r when stereo is demodulated in order to optimize the signal level at dbx block input (steps of 0.02 db): 1000 0000: -2.56 db ... 0000 0000: 0 db 0000 0001: 0.02 db ... 0111 1111: 2.54 db 76543210 btsc_fine_prescale_sap[7:0] (s) r/w [7:0] set the preschool of the signal coming fr om the demodulator when sap is demodulated in order to optimize the signal level at d bx block input (steps of 0.02 db): 1000 0000: -2.56 db ... 0000 0000: 0 db 0000 0001: 0.02 db ... 0111 1111: 2.54 db 76543210 fine_pres cale_sele ct_sap dbx_dematrix[1:0] dbx_on deemphasis_ch1[1:0] deemphasis_ch0[1:0] ro note: this register is controlled by autostandard and is forced by default to read-only mode. [7] select the prescale value to apply on second channel before dbx: 0: stereo presca le (register 90h) 1: sap prescale (register 91h) www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 78/167 dc_removal dc removal address: 93h type: ro reset: 0011 0000 [6:5] select l/r dematrix for stereo standard 00: no dematrixing (mono or sap) 01: l/r dematrix (stereo): l= ch0+(ch1)/2, r=ch0-(ch1)/2 10: reserved 11: reserved [4] 0: dbx noise reduction not active 1: dbx noise reduction active on second channel (stereo or sap) [3:2] select the de-emphasis for demodulator second channel: 00: no de-emphasis 01: 25 s de-emphasis 10: 50 s de-emphasis 11: 75 s de-emphasis [1:0] select the de-emphasis for demodulator first channel: 00: no de-emphasis 01: 25 s de-emphasis 10: 50 s de-emphasis 11: 75 s de-emphasis 76543210 00 dbx_filter_s elect deemphasis_ filter_selec t 0 dc_demod_p ost_on dc_demod_pr e_on dc_scart_on ro [7:6] reserved [5] select the type of filter used in the dbx block: 0: 1st order filter de-emphasis 1: 2nd order filter de-emphasis [4] select the type of filter used in the de-emphasis block 0: 1st order filter de-emphasis 1: 2nd order filter de-emphasis [3] reserved [2] control the dc removal placed on the demod path, after the dbx block: 0: dc removal off 1: dc removal on [1] control the dc removal placed on the demod path, before the dbx block: 0: dc removal off 1: dc removal on [0] control the dc removal placed on the scart path: 0: dc removal off 1: dc removal on www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 79/167 10.12 audio preprocessing and selection prescale_demod_mono prescale for demod mono address: 94h type: r/w reset: 0000 0000 prescale_demod_stereo prescale for stereo demodulation address: 95h type: r/w reset: 0000 0000 76543210 prescale_de mod_select_ sap prescale_demod_mono[6:0] (s) r/w note: the following register bit is controlled by autostandard and is forced by default to read-only mode. [7] select the prescale value to apply on channel 0 (mono/stereo): 0: apply stereo prescale (95h) to the dem odulated signal. to be used in case of stereo demodulation. 1: apply mono prescale (94h) on left channel and sap prescale (96h) on right channel to the demodulated signal. to be used in case of mono or sap demodulation. [6:0] set the prescale of the signal coming from the demodulator wh en mono (channel 0): 110 1000: 12 db ... 000 0000: 0 db 000 0001: 0.5 db ... 011 0000: 24 db 76543210 0 prescale_demod_stereo[6:0] (s) r/w [7] reserved [6:0] sets the prescale value of the stereo signal coming from the demodulator (channels 0 and 1): 110 1000: -12 db ... 000 0000: 0 db 000 0001: 0.5 db ... 011 0000: 24 db www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 80/167 prescale_demod_sap prescale for sap demodulation address: 96h type: r/w reset: 0000 0000 prescale_scart prescale for scart address: 97h type: r/w reset: 0000 0000 prescale_i2s0 prescale for i2s0 address: 98h type: r/w reset: 0000 0000 76543210 0 prescale_demod_sap[6:0] (s) r/w [7] reserved [6:0] set the prescale of the signal coming from the demodulator when sap (channel 0): 110 1000: -12db ... 000 0000: 0db 000 0001: 0.5db ... 011 0000: 24db 76543210 0 prescale_scart[6:0] (s) r/w [7] reserved [6:0] set the prescale of the signal coming from the scart adc: 110 1000: -12db ... 000 0000: 0db 000 0001: 0.5db ... 011 0000: 24db 76543210 0 prescale_i2s0[6:0] (s) r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 81/167 prescale_i2s1 prescale for i2s1 address: 99h type: r/w reset: 0000 0000 prescale_i2s2 prescale for i2s2 address: 9ah type: r/w reset: 0000 0000 [7] reserved [6:0] set the prescale of the signal coming from the i 2 s0 (src input or i2s0 in multi-channel input mode): 110 1000: -12db ... 000 0000: 0db 000 0001: 0.5db ... 011 0000: 24db 76543210 0 prescale_i2s1[6:0] (s) r/w [7] reserved [6:0] set the prescale of the signal coming from the i2s1 (i 2s1 in mult-channel input mode): 110 1000: -12db ... 000 0000: 0db 000 0001: 0.5db ... 011 0000: 24db 76543210 0 prescale_i2s2[6:0] (s) r/w [7] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 82/167 peak_detector peak detector address: 9bh type: ro reset: 0000 0000 [6:0] set the prescale of the signal coming from the i 2 s2 (delay input or i 2 s2 in multi-channel input mode): 110 1000: -12db ... 000 0000: 0db 000 0001: 0.5db ... 011 0000: 24db 76543210 0 peak_l_r_range[2:0] peak_det_input[2:0] peak_detect or_on ro [7] reserved [6:4] control the sensitivity of the ?left - right? peak measurement (register 0x9e). the difference between left and right signal is some times very small (for example, in the case of mono input), so you can multiply the ? left - right? peak measur ement in order to add precision: 000: left - right 001: left - right) x 2 010: left - right) x 4 011: left - right) x 8 100: left - right) x 16 101: left - right) x 32 110: left - right) x 64 111: left - right) x 128 [3:1] select the input on which the peak detector makes the measurement: 000: demod signal 001: i2s0 signal 010: i2s1 signal 011: i2s2 signal 100: scart signal 101: reserved 110: reserved 111: reserved [0] control the peak detector: 0: peak detector off 1: peak detector on www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 83/167 peak_l peak detector left channel l address: 9ch type: r/w reset: 0(000 0000) peak_r peak detector right channel address: 9dh type: r/w reset: 0(000 0000) 76543210 overload_l peak_l[6:0] (s) r/w [7] this bit is set to 1 by the dsp when the left peak detector reaches its maximum value (0x7f). it can be reset to 0. [6:0] displays the absolute peak le vel of the left channel of the au dio source selected. the measured value is updated continuously every 64 ms. the range varies linearly from the full scale (0 db) down to 1/256 of the full scale (-48 db). 000 0000: <-36dbfs ... 000 0001: -36dbfs ... 000 0011: -30dbfs ... 000 0111: -24dbfs ... 000 1111: -18dbfs ... 001 1111: -12dbfs ... 111 1111: 0dbfs 76543210 overload_r peak_r[6:0] (s) r/w [7] this bit is set to 1 by the dsp when the righ t peak detector reaches its maximum value (0x7f). it can be reset to 0. www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 84/167 peak_l_r peak detector left minus right channel l address: 9eh type: r/w reset: 0(000 0000) [6:0] displays the absolute peak level of the right channel of the audio source selected. the measured value is updated continuously every 64 ms. the range varies linearly from the full scale (0 db) down to 1/256 of the full scale (-48 db). 000 0000: <-36dbfs ... 000 0001: 36dbfs ... 000 0011: -30dbfs ... 000 0111: -24dbfs ... 000 1111: -18dbfs ... 001 1111: -12dbfs ... 011 1111: -6dbfs ... 111 1111: 0dbfs 76543210 overload_l_ r peak_l_r[6:0] (s) r/w [7] this bit is set to 1 by the dsp when the ? left-right? peak detector re aches its maximum value (0x7f). it can be reset to 0. [6:0] displays the difference between l and r (l - r) channels for the audio source selected: 000 0000: -36dbfs ... 000 0001: -36dbfs ... 000 0011: -30dbfs ... 000 0111: -24dbfs ... 000 1111: -18dbfs ... 001 1111: -12dbfs ... 011 1111: -6dbfs ... 111 1111: 0dbfs www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 85/167 10.13 matrixing downmix_mode downmix mode configuration address: 9fh type: r/w reset: 0111 1111 76543210 lt_rt_out_m ode mix_out_mode[2:0] lfe_in mix_in_mode[2:0] r/w [7] defines to format for downmix lt/rt output: 0: lt/rt pro logic compatible mode 1: l/r stereo mode [6:4] selects output channels configuration for downmix: see ta bl e 9 . [3] to select if lfe is inputted on i2s1 in multi-channel input mode: 0: no lfe on i2s1 input 1: lfe on i2s1 input [2:0] selects input channels configuration for downmix: see ta bl e 8 . table 8. downmix in modes parameter coding (bin) parameter field label function 000 mode11 not used 001 mode10 1/0 (c) 010 mode20 2/0 (l,r) 011 mode30 3/0 (l,r,c) 100 mode21 2/1 (l,r,s) 101 mode31 3/1 (l,r,c,s) 110 mode22 2/2 (l,r,ls,rs) 111 mode32 3/2 (l,r,c,ls,rs) table 9. downmix out modes parameter coding (bin) parameter field label function 000 mode20t 2/0 dolby surround (l,r) 001 mode10 1/0 (c) 010 mode20 2/0 (l,r) 011 mode30 3/0 (l,r,c) 100 mode21 2/1 (l,r,s) www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 86/167 downmix_dual_mode downmix dual mode configuration address: a0h type: r/w reset: 0000 0000 downmix_config downmix configuration address: a1h type: r/w reset: 0000 0001 101 mode31 3/1 (l,r,c,s) 110 mode22 2/2 (l,r,ls,rs) 111 mode32 3/2 (l,r,c,ls,rs) table 9. downmix out modes (continued) parameter coding (bin) parameter field label function 76543210 0 0 0 dual_on ls_dual_select[1:0] ltrt_dual_select[1:0] r/w [7:5] reserved [4] selects dual mode for downmix bloc in case of dual language (in dual mode, input and output mode are forced to 2_0): 0: standard downmix 1: downmix in dual mode [3:2] selects the language for ls output in case of dual mode: 00: stereo 01: left mono 10: right mono 11: left + right mix [1:0] selects the language for ltrt output in case of dual mode: 00: stereo 01: left mono 10: right mono 11: left + right mix 76543 210 0 0 srnd_factor[1:0] center_factor[1:0] lr_upmix normalize r/w [7:6] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 87/167 audio_matrix1 audio matr ix 1 configuration address: a2h type: r/w reset: 0010 0010 audio_matrix2 audio matr ix 2 configuration address: a3h type: r/w reset: 0001 0010 [5:4] 00: -3 db 01: -4.5 db 10: -6 db 10: -6 db [3:2] 00: -3 db 01: -4.5 db 10: -6 db 11: -4.5 db [1] 0: up mixing disabled 1: up mixing enabled (dts specified) [0] 0: normalization disabled 1: normalization enabled 76543210 0 0 hp_out ls_out r/w [7:6] reserved [5:3] select the source to output on hp. see ta bl e 1 0 . [2:0] select the source to output on ls. see ta bl e 1 0 . 765432 0 0 0 scart2_out scart1_out r/w [7:6] reserved [5:3] select the source to output on scart2: see ta bl e 1 0 . [2:0] select the source to output on scart1: see ta bl e 1 0 . www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 88/167 audio_matrix3 audio matr ix 3 configuration address: a4h type: r/w reset: 0001 0010 channel_matrix_ls channel matrix configuration for ls address: a5h type: r/w reset: 0000 0000 76543210 0 0 spdif_out delay_out r/w [7:6] reserved [5:3] select the source to output on spdif. see ta bl e 1 0 . [2:0] select the source to output on delay. see ta bl e 1 0 . table 10. audiomatrix input sources parameter coding (bin) parameter field label function 000 mute mute output 001 delay delay input 010 demod btsc demod input 011 ltrt downmix ltrt input 100 i 2 s i2s input 101 scart scart input 110 - reserved 111 - reserved 7654321 0 autostd_ctr l_ls autostd_ctr l_spdif 0 0 0 cm_matrix_ls[2:0] r/w [7] if this bit is activated, au tostandard algorithm auto matically selects the appropriate matrixing (bits[2:0]) for ls output channels depending on the detected standard (see ta b l e 1 2 ). 0: manual matrix selection 1: automatic matrix selection if autostandard is on note: automatic matrix selection must be used only when the demod signal is directed to the matrix. www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 89/167 channel_matrix_hp channel matrix configuration for hp address: a6h type: r/w reset: 0000 0000 channel_matrix_scart channel matrix configuration for scart address: a7h type: r/w reset: 0000 0000 [6] if this bit is activated, autostandard algorithm will select automatically the appropriate matrixing (bits[2:0]) for spdif output channel s depending on the detected standard (see ta b l e 1 2 ). 0: manual matrix selection 1: automatic matrix selection if autostandard is on note: automatic matrix selection must be used only when the demod signal is directed to the matrix. [5:3] reserved [2:0] select the matrixing for the ls channels. see ta b l e 1 1 . 76543210 autostd_ctr l_hp cm_source_hp[1:0] cm_position_hp[1:0] cm_matrix_hp[2:0] r/w [7] if this bit is activated, autostandard algorithm will select automatically the appropriate matrixing (bits[2:0]) for hp output channels depending on the detected standard (see ta b l e 1 2 ). 0: manual matrix selection 1: automatic matrix selection if autostandard is on note: automatic matrix selection must be used only when the demod signal is directed to the matrix. [6:5] select the source to copy on hp channel. see ta b l e 1 3 . [4:3] select the position for the hp matrix. see figure 4 00 = position 0 01 = position 1 10 = position 2 11 = position 3 [2:0] select the matrixing for the hp channels. see ta bl e 1 1 . 76543210 autostd_ctr l_scart cm_source_scart[1:0] cm_position_scart[1:0] cm_matrix_scart[2:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 90/167 channel_matrix_scartaux channel matr ix configuration for scartaux address: a8h type: r/w reset: 0000 0000 [7] if this bit is activated, the autostandard algorit hm automatically selects the appropriate matrixing (bits[2:0]) for scart output channels depending on the detected standard (see ta b l e 1 2 ). 0: manual matrix selection 1: automatic matrix selection must be used on ly when demod signal is directed to the matrix. [6:5] select the source to copy on scart channel. see ta bl e 1 3 . [4:3] select the position for the scart matrix. see figure 4 00 = position 0 01 = position 1 10 = position 2 11 = position 3 [2:0] select the matrixing for the scart channels. see ta b l e 1 1 . 7654 3210 autostd_ctr l_scartaux cm_source_scartaux[1:0] cm_position_scartaux[1:0] cm_matrix_scartaux[2:0] r/w [7] if this bit is activated, the autostandard algorithm automat ically selects the appropriate matrixing (bits[2:0]) for scartaux output c hannels depending on the detected standard (see ta b l e 1 2 ). 0: manual matrix selection 1: automatic matrix selection if autostandard is on note: automatic matrix selection must be used on ly when the demod signal is directed to the matrix. [6:5] select the source to copy on scartaux channel. see ta b l e 1 3 . [4:3] select the position for the scartaux matrix. see figure 4 . 00 = position 0 01 = position 1 10 = position 2 11 = position 3 [2:0] select the matrixing for the scartaux channels. see ta b l e 1 1 . www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 91/167 channel_matrix_spdif channel ma trix configuration for spdif address: a9h type: r/w reset: 0000 0000 76543210 cm_source_spdif[2:0] cm_position_spdif[1:0] cm_matrix_spdif[2:0] r/w [7:5] select the source to copy on spdif channel. see ta bl e 1 3 . [4:3] select the position for the spdif matrix. see figure 4 . 00 = position 0 01 = position 1 10 = position 2 11 = position 3 [2:0] select the matrixing for the spdif channels. see ta bl e 1 1 . table 11. channel matrix modes parameter coding (bin) parameter field label function 000 bypass bypass stereo signal 001 left only copy left signal on both channels 010 right only copy right signal on both channels 011 left + right mix copy (left + right)/2 on both channels 100 swap swap channel (left = right, right = left) 101 - reserved 110 - reserved 111 - reserved table 12. automatic channel matrix modes standard detected by autostandard mono_sap_ctrl_matrix reg 0x8a, bit[6] value = 0 mono_sap_ctrl_matrix reg 0x8a, bit[6] value = 1 left output right output left output right output mono mono signal mono signal mono signal mono signal stereo left signal right signal left signal right signal sap sap signal sap signal mono signal sap signal table 13. channel matrix source selection parameter coding (bin) parameter field label function 000 bypass bypass stereo signal coming from audio matrix 001 ls channels copy signal from ls channels www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 92/167 demod_dc_level dc level on demod fm mono input address: aah type: ro reset: 0000 0000 10.14 audio processing av_delay_config av delay configuration address: adh type: r/w reset: 0000 0000 010 hp channels copy signal from hp channels 011 c/sub channels copy signal from c/sub channels (only available on spdif channel matrix) 100 ls/rs channels copy signal from ls/rs channels (only available on spdif channel matrix) 101 - reserved 110 - reserved 111 - reserved table 13. channel matrix source selection (continued) parameter coding (bin) parameter field label function 76543210 demod_dc_level[7:0] (s) ro [7:0] displays the amount of the dc component in t he signal coming from the fm mono channel. this dc level can be used to implem ent carrier offset compensation. 76543210 000000 dolby_delay _on av_delay_on r/w [7:2] reserved [1] must be set to 1 to use the center, left srnd and right srnd delays for pro logic decoder multi- channel output. note: this value must be updated when av_delay_on = 0. [0] 0: no av delay 1: av delay is active www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 93/167 note: see ta bl e 1 4 for audio/video delay configuration. av_delay_time_ls av delay ls configuration address: aeh type: r/w reset: 0000 0000 note: see ta bl e 1 4 for audio/video delay configuration. av_delay_time_hp av delay hp configuration address: afh type: r/w reset: 0000 0000 note: 1 see ta bl e 1 4 for audio/video delay configuration. 2 the sum of av_delay_time_ls and av_delay_time_hp must not exceed: ? 177 (116.82 ms) if dolby_delay_on = 0 ? 100 (66.66 ms) if dolby_delay_on = 1 76543210 av_delay_time_ls[7:0] r/w [7:0] set the delay time for ls channel. 0000 0000: 0 ms 0000 0001: 0.66 ms ... 1011 0001: 116.82 ms (max) note: this value must be updated when av_delay_on = 0. 76543210 av_delay_time_hp[7:0] r/w [7:0] set the delay time for hp channel. 0000 0000: 0 ms 0000 0001: 0.66 ms ... 1011 0001: 116.82 ms (max) note: this value must be updated when av_delay_on = 0. www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 94/167 . pro_logic2_control dolby pro logic 2 mode configuration address: b0h type: r/w reset: 0000 0000 table 14. audio/video delay (lip sync) configuration input source register values output av_delay_co nfig(adh) av_delay_ti me_ls(aeh) av_delay_ti me_hp(afh) pcm_srnd_de lay(b5h) pcm_center_ delay(b6h) ls_l ls_r hp_r/l scart_ l scart_ r dolby _dela y_ on av_ delay _on av_delay_ time_ls[7:0] av_delay_ time_hp[7:0] dolby_delay_ srnd[4:0] dolby_delay_ center[3:0] source sif- scart i2s source sif- scart i2s source sif- scart i2s source sif- scar t i2s source sif- scart i2s sif or scart or i2s (48khz) 0 1 00000000 0 00000000 0 xxx00000 0 xxxx0000 0 0 0 0 0 0 0 1 10110001 117 00000000 0 xxx11110 30 xxxx1010 10 117 117 0 0 0 0 1 00000000 0 10110001 117 xxx00000 0 xxxx0000 0 0 0 117 0 0 0 1 01011000 58 01011000 58 xxx00000 0 xxxx0000 0 58 58 58 0 0 1 1 10110001 117 00000000 0 xxx00000 0 xxxx0000 0 66 66 0 0 0 1 1 00000000 0 10110001 117 xxx11110 30 xxxx0000 10 0 0 66 0 0 1 1 01011000 58 01011000 58 xxx00000 0 xxxx0000 0 58 58 8 0 0 1 1 01011000 58 01011000 58 xxx11110 30 xxxx0000 0 58 58 8 0 0 1 1 01011000 58 01011000 58 xxx00000 0 xxxx1010 10 58 58 8 0 0 1 1 01011000 58 01011000 58 xxx11110 30 xxxx1010 10 58 58 8 0 0 76543210 pl2_lfe pl2_output_downmix[2:0] pl2_modes[2:0] pl2_active r/w [7] 0: reset the lfe channel 1: bypass the lfe channel [6:4] 000: not applicable 001: not applicable 010: not applicable 011: 3/0 output mode (l,r,c) 100: 2/1 output mode (l,r,ls - phantom) 101: 3 /1 output mode (l,r,c,ls) 110: 2/2 output mode (l,r,ls,rs - phantom) 111: 3/2 output mode (l,r,c,ls,rs) [3:1] 000: pro logic 1 emulation 001: virtual 010: music 011: movie (standard) 100: matrix 101: custom 110: not applicable 111: not applicable [0] 0: dolby pro logic 2 is not active 1: dolby pro logic 2 is active www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 95/167 pro_logic2_config dolby pro logic 2 configuration address: b1h type: r/w reset: 0000 0000 pro_logic2_dimension dolby pro logic 2 dimension address: b2h type: r/w reset: 0000 0000 76543210 pl2_lfe0 0 0 pl2_srnd_filter[1:0] pl2_rs_pola rity pl2_panoram a pl2_autobala nce r/w [7] 0: reset the lfe channel 1: bypass the lfe channel [6:5] reserved [4:3] 00: off 01: shelf 10: 7-khz lp 11: not applicable [2] 0: rs polarity normal 1: rs polarity inverted [1] 0: panorama off 1: panorama on [0] 0: autobalance off 1: autobalance on 76543210 0 pl2_c_width 0 pl2_dimension r/w [7] reserved [6:5] pro logic 2 center width: 000: 0, no spread 001: 20.8 010: 28 011: 36 100: 54 101: 62 110: 69.2 111: 90, phantom [3] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 96/167 pro_logic2_level dolby pro logic 2 input level address: b3h type: r/w reset: 0000 0000 noise_generator pink noise generator address: b4h type: r/w reset: 0000 0000 [2:0] pro logic 2 dimension: 000: -3, most surround 001: -2 010: -1 011:: 0, neutral 100: 1 101: 2 110: 3, most center 111: not used 76543210 pl2_level r/w [7:0] input gain attenuation: 0000 0000: 0 db 0000 0001:-0.5 db ... 1111 1111: -127.5 db 76543210 10_db_attenu at e sright_noise sleft_noise sub_noise center_nois e right_noise left_noise noise_on r/w [7] 0: noise is output with full range 1: noise is output with a 10db attenuation [6] 1: generates noise on ls right surround output [5] 1: generates noise on ls left surround output [4] 1: generates noise on ls subwoofer output [3] 1: generates noise on ls center output [2] 1: generates noise on ls right output [1] 1: generates noise on ls left output www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 97/167 pcm_srnd_delay dolby surround delay address: b5 type: r/w reset: 0000 0000 note: 1 see ta bl e 1 4 for audio/video delay configuration. 2 to use this feature, set the dolby_delay_on bit to 1 in register av_delay_config (adh). pcm_center_delay dolby center delay address: b6h type: r/w reset: 0000 0000 note: 1 see ta bl e 1 4 for audio/video delay configuration. 2 to use this feature, set the dolby_delay_on bit to 1 in register av_delay_config (adh). [0] 0: noise generation not active 1: noise generation active 76543210 0 0 0 dolby_delay_srnd[4:0] r/w [7:5] reserved [4:0] surround channel delay: range: 0 to 30 (in ms) 76543210 0 0 0 0 dolby_delay_center[3:0] r/w [7:4] reserved [3:0] center channel delay: range: 0 to 10 (in ms) www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 98/167 trusrnd_control srs trusurround control address: b7h type: r/w reset: 0000 0000 note: using trusurround xt: - implementation of trusurround xt is done by setting the trusrnd_on bit to 1. - trusurround xt mode must be selected by trusrnd_input_ mode[3:0] bits. - activation or non-activation of trusurround xt must be done by using the trusrnd_mode bit. 76543210 dialog_clari ty_on headphone_ on trusrnd_input_ mode[3:0] trusrnd_byp ass trusrnd_on r/w [7] dialog clarity: 0: dialog clarity off 1: dialog clarity on note: the dialog clarity level is set in register 0xb8: trusrnd_dc_elevation [6] process the sound especially for headphones. this option must be selected only if the trusurround sound is redirected to the headphon e output using the hp channel matrix. 0:standard mode for loudspeaker output 1:headphone mode for headphone output only [5:2] 0000: mono on center channel 0001: mono on left channel 0010: l/r stereo (srs mode) 0011: l/r/s (srs mode, pro logic 1 process) 0100: l/r/ls/rs (srs mode) 0110: l/r/c/s (trusurround mode, pro logic 1 process) 0111: l/r/c/ls/rs (trusurround mode) 1000: lt/rt (trusurround mode) 1001: l/r/c/ls/rs (srs mode, bs digital broadcast) 1010: l/r/c/ls/rs (trusurround, pro logic 2 music mode) [1] bypass the trusurround effect by applying a simple downmix on input channels. 0: trusurround mode 1: bypass mode (downmix to 2 channels) [0] 0: trusurround off 1: trusurround on www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 99/167 trusrnd_dc_elevation set dialog clarity level address: b8h type: r/w reset: 0000 1100l trusrnd_input_gain input gain for trusurround address: b9h type: r/w reset: 0000 0000 trubass_ls_control ls conf iguration for srs trubass address: bah type: r/w reset: 0000 0110 76543210 trusrnd_dc_elevation[7:0] r/w [7:0] dialog clarity elevation: 0000 0000: 0 db 0000 0001: -0.5 db ... 1111 1111: -127.5 db 7654 3210 trusrnd_input_gain[7:0] r/w [7:0] input gain attenuation: 0000 0000: 0 db 0000 0001: -0.5 db ... 1111 1111: -127.5 db 76543210 0000 trub ass_ls_size[2:0] trubass_ls_ on r/w [7:4] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 100/167 trubass_ls_level srs trubass ls level address: bbh type: r/w reset: 0000 1001 trubass_hp_control srs trubass hp configuration address: bch type: r/w reset: 0000 0110 [3:1] 000: lf response at 40 hz 001: lf response at 60 hz 010: lf response at 100 hz 011: lf response at 150 hz 100: lf response at 200 hz 101: lf response at 250 hz 110: lf response at 300 hz 111: lf response at 400 hz [0] 0: ls trubass off 1: ls trubass on 76543210 trubass_ls_level[7:0] r/w [7:0] defines the amount of srs trubass effect for ls outputs: 0000 0000: 0 db 0000 0001: -0.5 db ... 1111 1111: -127.5 db 76543210 srs_tsxt_gai n_on 0 0 0 trubass_hp_size[2:0] trubass_hp_ on [7] apply the trusurround gain (register 0xb9) to the trubass input block. this gain must be applied only if the trusurround signal has been redirected to the trubass hp via the hp channel matrix. 0: sxt input gain is not applied 1: tsxt input gain is applied. (t his configuration must be used if the ls signal processed with tsxt is redirected to the hp channel) [6:4] reserved www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 101/167 trubass_hp_level srs trubass hp level address: bdh type: r/w reset: 0000 1001 svc_ls_control smart volume control for ls address: beh type: r/w reset: 0000 0010 [3:10] 000: lf response at 40 hz 001: lf response at 60 hz 010: lf response at 100 hz 011: lf response at 150 hz 100: lf response at 200 hz 101: lf response at 250 hz 110: lf response at 300 hz 111: lf response at 400 hz [0] 0: hp trubass off 1: hp trubass on 76543210 trubass_hp_level[7:0] r/w [7:0] defines the amount of srs trubass effect for hp outputs: 0000 0000: 0 db 0000 0001: -0.5 db ... 1111 1111: -127.5 db 76543210 0000svc_ls_input[1:0]svc_ls_ampsvc_ls_on r/w [7:4] reserved [3:2] select input for peak detection in multi-channel mode: 00: left/right 01: center 10: left/right/center 11: not used [1] 0: 0 db amplification in auto-mode 1: +6 db amplific ation in auto-mode [0] 0: manual mode (simple prescaler) 1: automatic mode www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 102/167 svc_ls_time_th smart volume control parameters for ls address: bfh type: r/w reset: 1001 1000 76543210 svc_ls_time[2:0] svc_ls_threshold[4:0] (s) r/w [7:6] time constant for amplification (6-db gain step) in automatic mode: 000: 30 ms 001: 200 ms 010: 500 ms 011: 1 s 100: 16 s 101: 32 s 110: 64 s 111: 128 s [4:0] (s) see ta bl e 1 5 and ta b l e 1 6 . table 15. gain (threshold field) values in manual mode manual mode gain (db) manual mode gain (db0 00101 +15.5 11101 -8.5 00100 +12 11100 -12 00011 +9.5 11011 -14.5 00010 +6 11010 -18 00001 +3.5 11001 -20.5 00000 0 11000 -24 11111 -2.5 10111 -26.5 11110 -6 10110 -30 table 16. threshold values in automatic mode automatic mode threshold (db) automatic mode threshold (db) 11111 -2.5 11010 -18 11110 -6 11001 -20.5 11101 -8.5 11000 -24 11100 -12 10111 -26.5 11011 -14.5 10110 -30 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 103/167 svc_ls_gain make-up gain for svc ls address: c0h type: r/w reset: 0000 0000 svc_hp_control smart volume control for hp address: c1h type: r/w reset: 0000 0010 svc_hp_time_th smart volume control parameters for hp address: c2h type: r/w reset: 1001 1000 7654321 0 0 0 svc_ls_gain[5:0] r/w [7:6] reserved [5:0] set ?make-up? gain applied at svc ls output: 000000: +0 db 000001:+ 0.5 db ... 101110: +23 db 101111: +23.5 db 110000: +24 db 76543210 0 0 0 0 0 0 svc_hp_amp svc_hp_on r/w [7:2] reserved [1] 0: 0 db amplific ation in auto-mode 1: +6 db amplification in auto-mode [0] 0: manual mode (simple prescaler) 1: automatic mode 76543210 svc_hp_time[2:0] svc_hp_threshold[4:0] (s) r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 104/167 svc_hp_gain make-up gain for svc hp address: c3h type: r/w reset: 0000 0000 widesrnd_control st widesurround sound control l address: c4h type: r/w reset: 0000 0100 [7:5] time constant for amplificati on (6-db gain step) in automatic mode: 000: 30 ms 001: 200 ms 010: 500 ms 011: 1 s 100: 6 s 101: 32 s 110: 64 s 111: 128 s [4:0] (s) see ta b l e 1 5 and ta bl e 1 6 76543210 0 0 svc_hp_gain[5:0] r/w [7:6] reserved [5:0] set ?make-up? gain applied at svc hp output: 000000: +0 db 000001: 0.5 db ... 101110: +23 db 101111: +23.5 db 110000: +24 db 7654 321 0 00000 widesrnd_st ereo widesrnd_mo de widesrnd_on r/w [7:3] reserved [2] st widesurround sound stereo mode: 0: st widesurround sound in mono mode (default) 1: st widesurround sound in stereo mode www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 105/167 widesrnd_freq st widesurround sound frequency address: c5h type: r/w reset: 0001 0101 widesrnd_level st widesurround sound gain address: c6h type: r/w reset: 1000 0000 [1] st widesurround sound stereo mode: 0: movie mode 1: music mode [0] st widesurround sound enable: 0: st widesurround sound is disabled 1: st widesurround sound is enabled 76543210 0 0 widesrnd_bass[1:0] widesrnd_medium[1:0] widesrnd_treble[1:0] r/w [7:6] reserved [5:4] defines the bass frequency effect for st wi desurround sound. programmab le values are listed in ta bl e 1 7 . [3:2] defines the medium frequency effect for st widesurround sound in movie or mono mode (no effect in music mode). programm able values are listed in ta bl e 1 7 . [1:0] defines the treble frequency effect for st widesurround sound in movie or mono mode (no effect in music mode). programm able values are listed in ta bl e 1 7 . table 17. phase shifter center frequencies phase shifter center frequency bass_freq[1:0] medium_freq[1:0] treble_freq[1:0] 00 40 hz 202 hz 2 khz 01 (default) 90 hz 416 hz 4 khz 10 120 hz 500 hz 5 khz 11 160 hz 588 hz 6 khz 76543210 widesrnd_gain[7:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 106/167 omnisurround_control st omnisurround configuration address: c7h type: r/w reset: 0000 1100 [7:0] defines the st widesurround so und component gain in linear scale: level (%) 1000 0000 (default) 100% 0111 1111 99.2% 0111 1110 98.4% 0111 1101 97.6% 0000 0100 3.1% 0000 0011 2.3% 0000 0010 1.6% 0000 0001 0.8% 0000 0000 0% 76543210 st_voice[1:0] srnd_phase_i nv omnisrnd_input_mode[3:0] omnisrnd_on r/w [7:6] 00: off 01: low 10: mid 11: high [5] invert right surround phase in 2_2 or 3_2 input mode: 0: right surround phase not inverted 1: right surround phase inverted [4:1] 0000: mono on center channel 0001: mono on left channel 0010: l/r stereo 0011: l/r/s 0100: l/r/ls/rs 0101: l/r/c 0110: l/r/c/s 0111: l/r/c/ls/rs 1000: lt/rt (passive matrix) [0] 0: omnisurround off 1: omnisurround on www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 107/167 dynamic_bass_ls st dynamic bass for ls address: c8h type: r/w reset: 0110 0010 dynamic_bass_hp st dynamic bass for hp address: c9h type: r/w reset: 0110 0010 76543210 ls_bass_level[4:0] ls_bass_freq[1:0] ls_dyn_bass_ on r/w [7:3] st dynamic bass output gain: 00000: + 0db 00001: +0.5db ... 11101: +14.5db 11110: +15db 11111: +15.5db [2:1] 00: 100-hz cut-off frequency 01: 150-hz cut-off frequency 10: 200-hz cut-off frequency 11: 250-hz cut-off frequency [0] 0: st dynamic bass off 1: st dynamic bass on 76543210 hp_bass_level[4:0] hp_bass_freq[1:0] hp_dyn_bass _on r/w [7:3] st dynamic bass output gain: 00000: +0db 00001: +0.5db ... 11101: +14.5db 11110: +15db 11111: +15.5db [2:1] 00: 100-hz cut-off frequency 01: 150-hz cut-off frequency 10: 200-hz cut-off frequency 11: 250-hz cut-off frequency [0] 0: st dynamic bass off 1: st dynamic bass on www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 108/167 eq_bt_ctrl loudspeakers equalizer control address: cch type: r/w reset: 0000 0001 ls_eq_bandx loudspeakers equalizer gain for bandx address: cdh to d1h type: r/w reset: 0000 0000 note: with positive equalizer settings, internal clipping can occur even with an overall volume of less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain 76543210 0 0 0 0 0 hp_bt_on ls_eq_bt_sw ls_eq_on r/w [7:3] reserved [2] bass-treble for hp enable 0: bass-treble is disabled 1: bass-treble is enabled [1] 5- band equalizer or bass-treble for ls selection 0: 5-band equalizer is selected for loudspeakers. 1: bass-treble is selected for loudspeakers. [0] 5-band equalizer/bass-ttreble for ls enable 0: 5-band equalizer/bass-treble is disabled 1: 5-band equalizer/bass-treble is enabled 76543210 eq_bandx[7:0] r/w [7:0] bandx gain adjustment within a range from -12 db to +12 db in steps of 0.25 db. band1: 100 hz band2: 330 hz band3: 1 khz band4: 3.3 khz band5: 10 khz. see ta b l e 1 8 . www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 109/167 ls_bass_gain loudspeakers bass gain address: d2h type: r/w reset: 0000 0000 note: with positive bass/treble settings, internal clipping can occur even with an overall volume of less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set bass/treble bands to a value that, in conjunction with volume, would result in an overall positive gain. ls_treble_gain loudspeakers treble gain address: d3h type: r/w reset: 0000 0000 table 18. loudspeakers equalizer/bass-treble gain values (and headphone bass-treble gain values) value gain g (db) 00110000 +12 00101111 +11.75 00101110 +11.50 ................ ..... 00000000 (default) 0 ................ ..... 11010010 -11.50 11010001 -11.75 11010000 -12 7654 3210 ls_bass[7:0] r/w [7:0] gain tuning of loudspeakers bass frequency gain can be programmed within a range betw een +12 db and -12 db in steps of 0.25 db. programmable values are listed in ta bl e 1 8 . 76543210 ls_treble r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 110/167 note: with positive bass/treble settings, internal clipping can occur even with an overall volume of less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set bass/treble bands to a value that, in conjunction with volume, would result in an overall positive gain. hp_bass_gain headphone bass gain address: d4h type: r/w reset: 0000 0000 note: with positive bass/treble settings, internal clipping can occur even with an overall volume of less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set bass/treble bands to a value that, in conjunction with volume, would result in an overall positive gain. hp_treble_gain headphone treble gain address: d5h type: r/w reset: 0000 0000 note: with positive bass/treble settings, internal clipping can occur even with an overall volume of less than 0 db. this will lead to a clipped output signal. therefore, it is not recommended to set bass/treble bands to a value that, in conjunction with volume, would result in an overall positive gain. [7:0] gain tuning of loudspeakers treble frequency. gain can be programmed within a range between +12 db and -12 db in steps of 0.25 db. programmable values are listed in ta b l e 1 8 . 76543210 hp_bass[7:0] r/w [7:0] gain tuning of headphone bass frequency. gain can be programmed within a range between +12 db and -12 db in steps of 0.25 db. programmable values are listed in ta b l e 1 8 . 7654 3210 hp_treble r/w [7:0] gain tuning of headphone treble frequency. gain can be programmed within a range between +12 db and -12 db in steps of 0.25 db. programmable values are listed in ta b l e 1 8 . www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 111/167 output_bass_mngt bass redirection address: d6h type: r/w reset: 1000 0000 76543210 bass_manage _on st_lfe_add dolby_prolo gic sub_active gain_switch ocfg_num[2:0] r/w [7] 0: bass management disabled 1: bass management enabled [6] add the signal coming from the lfe input (mul ti_i2s mode only) to t he calculated subwoofer signal: 0: no lfe channel to add 1: add lfe signal to the subwoofer computed signal [5] if bass management is used with the dolby pr o logic decoder, the surround channels must not be added to generate the subwoofer channel: 0: standard configuration (dolby digital compli ant), surround channels are used to generate the subwoofer channel. 1: dolby pro logic configuration, surround channels are not used to generate the subwoofer channel. [4] in some configurations the subwoofer signal can be redirected to l/r channels if there is no subwoofer output:. 0: no subwoofer output, the sub signal is added to l/r channels 1: subwoofer signal is output ted on subwoofer output. [3] gain switch available in some configurations: 0: level adjustment on 1: level adjustment off [2:0] select bass management configuration: 000: output configuration 0 001: output configuration 1 010: output configuration 2 011: output configuration 3 100: output configuration 4 (simplified configuration) 101: output configuration 5 (s tereo full bandwidth speakers) 110: output configuration 6 (stereo narrow bandwidth speakers) 111: not used www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 112/167 ls_loudness loudness configuration for ls address: d7h type: r/w reset: 0000 0100 hp_loudness loudness configuration for hp address: d8h type: r/w reset: 0000 0100 76543210 0 ls_loud_threshold[2:0] ls_loud_gain_hr[2:0] ls_loud_on [7] reserved [6:4] defines the volume threshold level at which the loudness effect is applied: 000: 0 db 001: -6 db 010: -12 db 011: -18 db 100: -24 db 101: -32 db 110: -36 db 111: -42 db [3:1] defines the amount of tr eble added by loudness effect: 000: 0 db 001: 3 db 010: 6 db 011: 9 db 100: 12 db 101: 15 db 110: 18 db 111: not used [0] 0: loudness is not active on ls output 1: loudness is active on ls output 76543210 0 hp_loud_threshold[2:0] hp_loud_gain_hr[2:0] hp_loud_on [7] reserved [6:4] defines the volume threshold leve l since which loudness effect is applied: 000: 0 db 001: -6 db 010: -12 db 011: -18 db 100: -24 db 101: -32 db 110: -36 db 111: -42 db www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 113/167 volume_modes set the volume modes address: d9h type: r/w reset: 1101 1111 [3:1] defines the amount of treble added by loudness effect: 000: 0 db 001: 3 db 010: 6 db 011: 9 db 100: 12 db 101: 15 db 110: 18 db 111: not used [0] 0: loudness is not active on hp output 1: loudness is active on hp output 76543210 anticlip_hp_ vol_clamp anticlip_ls_v ol_clamp 0 scart2_ volume_ mode scart1_ volume_ mode hp_ volume_ mode srnd_ volume_ mode ls_ volume_ mode r/w [7] the output level is clamped depending on the hp bas s-treble value to avoid any possible signal clipping on the hp output. 0: volume clamp on hp output is not active 1: volume clamp on hp output is active [6] the output level is clamped depending on the ls eq ualizer or ls bass-treble value to avoid any possible signal clipping on the ls output. 0: volume clamp on ls output is not active 1: volume clamp on ls output is active [5] reserved [4] volume mode for scart2 output: 0: independent 1: differential [3] volume mode for scart1 output: 0: independent 1: differential [2] volume mode for headphone output: 0: independent 1: differential [1] volume mode for surround output: 0: independent 1: differential [0] volume mode for ls output: 0: independent 1: differential www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 114/167 note: 1 for the use of volume and balance control please refer to figure 13 and figure 14 . 2 in differential mode the left register is used for volume control and the right register is used for balance control. ls_l_volume_msb loudspeaker left volume msb address: dah type: r/w reset: 1001 1000 ls_l_volume_lsb loudspeaker left volume lsb address: dbh type: r/w reset: 0000 0000 ls_r_volume_msb loudspeaker right volume msb address: dch type: r/w reset: 0000 0000 76543210 ls_l_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit left loudspeaker volume 76543210 0 0 0 0 0 0 ls_l_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit left loudspeaker volume 76543210 ls_r_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit right loudspeaker volume www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 115/167 ls_r_volume_lsb loudspeaker right volume lsb address: ddh type: r/w reset: 0000 0000 ls_c_volume_msb loudspeaker center volume msb address: deh type: r/w reset: 1001 1000 ls_c_volume_lsb loudspeaker center volume lsb address: dfh type: r/w reset: 0000 0000 76543210 0 0 0 0 0 0 ls_r_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit right loudspeaker volume 76543210 ls_c_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit center loudspeaker volume 76543210 000000ls_c_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit center loudspeaker volume www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 116/167 ls_sub_volume_msb loudspeaker subwoofer volume msb address: e0h type: r/w reset: 1001 1000 ls_sub_volume_lsb loudspeaker subwoofer volume lsb address: e1h type: r/w reset: 0000 0000 ls_sl_volume_msb loudspeaker left surround volume msb address: e2h type: r/w reset: 1001 1000 ls_sl_volume_lsb loudspeaker left surround volume lsb 7654 3210 ls_sub_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit subwoofer loudspeaker volume 76543210 000000ls_sub_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit subwoofer loudspeaker volume 76543 210 ls_sl_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit left surround loudspeaker volume 76543210 000000ls_sl_volume_lsb[1:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 117/167 address: e3h type: r/w reset: 0000 0000 ls_sr_volume_msb loudspeaker right surround volume msb address: e4h type: r/w reset: 0000 0000 ls_sr_volume_lsb loudspeaker right surround volume lsb address: e5h type: r/w reset: 0000 0000 ls_master_volume_msb loudspeaker master volume msb address: e6h type: r/w reset: 1110 1000 [7:2] reserved [1:0] 2 lsbs of the 10-bit left surround loudspeaker volume 76543210 ls_sr_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit right surround loudspeaker volume 76543210 000000ls_sr_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit right surround loudspeaker volume 76543210 ls_master_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bi t master loudspeaker volume www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 118/167 ls_master_volume_lsb loudspeak er master volume lsb address: e7h type: r/w reset: 0000 0000 hp_l_volume_msb headphone left volume msb address: e8h type: r/w reset: 1001 1000 hp_l_volume_lsb headphone left volume lsb address: e9h type: r/w reset: 0000 0000 76543210 000000ls_master_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit master loudspeaker volume 76543210 hp_l_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit left headphone volume 76543210 0 0 0 0 0 0 hp_l_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit left headphone volume www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 119/167 hp_r_volume_msb headphone right volume msb address: eah type: r/w reset: 0000 0000 hp_r_volume_lsb headphone right volume lsb address: ebh type: r/w reset: 0000 0000 aux_volume_index select the aux to apply volume address: ech type: r/w reset: 0000 0001 7654 321 0 hp_r_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit right headphone volume 76543210 000000hp_r_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit right headphone volume 76543210 0 0 0 0 0 0 aux_volume_select[1:0] r/w [7:2] reserved [1:0] select the output on which the aux_volume values will be applied: 00: no volume applied ( mandatory step to change selection from 01 to 10 ) 01: volume applied to scart1 output 10: volume applied to scart2 output 11: not used www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 120/167 aux_l_volume_msb auxiliary left volume msb address: edh type: r/w reset: 1101 1101 aux_l_volume_lsb auxiliary left volume lsb address: eeh type: r/w reset: 0000 0000 aux_r_volume_msb auxiliary right volume msb address: efh type: r/w reset: 0000 0000 aux_r_volume_lsb auxiliary right volume lsb 76543210 aux_l_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit left auxiliary volume 7654 3210 0 0 0 0 0 0 aux_l_volume_lsb[1:0] r/w [7:2] reserved [1:0] 2 lsbs of the 10-bit left auxiliary volume 7654321 0 aux_r_volume_msb[7:0] r/w [7:0] 8 msbs of the 10-bit right auxiliary volume 7654 3210 000000aux_r_volume_lsb[1:0] r/w www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 121/167 address: f0h type: r/w reset: 0000 0000 10.15 mute mute_software soft mute output by dsp address: f1h type: r/w reset: 1111 1111 [7:2] reserved [1:0] 2 lsbs of the 10-bit right auxiliary volume 76543210 hp_d_mute spdif_d_mute scart2_d_mu te scart1_d_mu te srnd_d_mute sub_d_mute c_d_mute ls_d_mute r/w [7] digital soft mute for hp output: 0: soft mute not active 1: soft mute active [6] digital soft mute for spdif output: 0: soft mute not active 1: soft mute active [5] digital soft mute for scart2 output: 0: soft mute not active 1: soft mute active [4] digital soft mute for scart1 output: 0: soft mute not active 1: soft mute active [3] digital soft mute for surround output: 0: soft mute not active 1: soft mute active [2] digital soft mute for subwoofer output: 0: soft mute not active 1: soft mute active [1] digital soft mute for center output: 0: soft mute not active 1: soft mute active [0] digital soft mute for loudspeaker output: 0: soft mute not active 1: soft mute active www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 122/167 10.16 beeper beeper_on set beeper on address: f2h type: r/w reset: 0000 0000 note: 1 if beeper_sound_selec t = 0 and beeper_continuous(reg 0xf3) is set to 1, the beeper_on needs to be set to 0 to stop the beeper sound; otherwise, the beeper is stopped automatically. 2 on beeper stop, the register 0xf2 is reset to 0. take care to set bit[2:1] on each beeper_on action. 3 beeper parameters cannot be changed when beeper is on. beeper_mode beeper control address: f3h type: r/w reset: 0100 0011 76543210 00000be eper_sound_select[1:0] beeper_on r/w [7:3] reserved [2:1] select the kind of sound generated by the beeper when beeper_on is set to 1: 00: square wave signal. frequency and de cay can be set in register 0xf4. 01: wood block natural sound 10: clic natural sound 11: bleep natural sound. [0] control beeper sound start/stop: 0: stop beeper 1: start beeper 7654 3210 beeper_decay[2:0] beeper_duration[1:0] beeper_cont inuous beeper_path r/w [7:5] control the decay of the envelope of the beeper sound: 000: short decay (sounds dry) ... 111: very long decay (sounds wet) www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 123/167 note: beeper parameters cannot be changed when beeper is on. beeper_freq_vol beeper fre quency and volume settings address: f4h type: r/w reset: 0111 0110 10.17 spdif output configuration spdif_out_channel_status spdif output channel configuration [4:3] defines beeper duration when beeper_continuous is set to 0: 00: 0.1 sec. 01: 0.25 sec. 10: 0.5 sec. 11: 1 sec. [2] sets beeper mode: 0: pulse mode selected, beeper_on is automatically reset to 0 after beeper_duration. 1: continuous mode selected, beeper_on must be set to 0 to stop the beeper sound. [1:0] sets the output channels when beeper is active: 00: no channels. 01: loudspeakers only. 10: headphone only. 11: loudspeakers and headphone selected. 76543210 beep_freq[2:0] beep_vol[4:0] r/w [7:5] defines the frequency of the beeper tone from 62.5 hz to 8 khz in octaves: 000: 62.5 hz 001: 125 hz 010: 250 hz 011: 00 hz (default) 100: 1 khz 101: 2 khz 110: 4 khz 111: 8 khz [4:0] defines the beeper volume from 0 to -93 db in steps of 3 db. 11111: 0 db (1 v rms ) . ... 11110: -3 db 00011 11101: -6 db 00010: -87 db ... 00001: -90 db 10000: -48 db (default) 00000: -93 db 765432 0 00000 spdif_copyri ght spdif_no_pc m spdif_consu mer_pro r/w www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 124/167 address: f5h type: r/w reset: 0000 0000 10.18 headphone configuration headphone_config headphone configuration address: f6h type: r/w reset: 0000 0010 [7:3] reserved [2] 0: copyright 1: no copyright [1] 0: pcm format 1: no pcm format [0] 0: consumer format 1: professional format 76543210 0 0 scartaux_out_select[1:0] hp_force hp_ls_mute hp_det_activ e hp_detected r/w [7:6] reserved [5:4] select scartaux output: 00: scartaux not output 01: scartaux signal output on c/sub dac 10: scartaux signal output on srnd/hp dac 11: not used [3] 1: force to output the hp signal (bypass surround) note: when hp is forced, irq5 and hp/srnd dac automatic mute are not active. [2] 0: when hp is detected and active, ls is not muted 1: when hp is detected and active, ls is muted [1] 0: hp detection is not active 1: hp detection is active, when hp detected, surround signal is bypassed and hp signal is outputted on hp [0] 1: when a signal is detected on hp_det pin www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 125/167 10.19 dac control dac_control dac control address: f7h type: r/w reset: 0001 1111 sw1_channels dac sw channel address: f8h type: r/w reset: 0000 0000 76543 210 0 0 spdif_mux dac_scart_m ute dac_shp_mut e dac_csub_mu te dac_lslr_mu te power_up r/w [7:6] reserved [5] redirect external or internal source i2s to i2s output: 0: internal source (pcm format) 1: external source on s/pdif_in pin [4] scart left/right analog soft mute: 0: soft mute not active 1: soft mute active [3] surround/hp left/right analog soft mute: 0: soft mute not active 1: soft mute active [2] center/subwoofer analog soft mute: 0: soft mute not active 1: soft mute active [1] ls left/right analog soft mute 0: soft mute not active 1: soft mute active [0] 0: dacs power off 1: power on 76543210 c_sub_sw sur_hp_sw scart_sw spdif_sw r/w [7:6] center/sub dac: 00: left/right channels non inverted 11: left/right channels inverted www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 126/167 sw2_channels spdif sw channel address: f9h type: r/w reset: 0000 0000 note: 1 to switch the outputs between non-inverted and inverted mode it is necessary to stop and start the dsp with the host_run bit while keeping registers_reset bit on (i 2 c register table not initialized). 2 these bits can be used to swap the outputs on corresponding dac outputs or on i 2 s outputs. 3 non-inverted or inverted modes are the same on all i2s outputs (i2s_data0, i2s0_data0, i2s0_data1. [5:4] surround/hp dac: 00: left/right channels non inverted 11: left/right channels inverted [3:2] scart dac: 00: left/right channels non inverted 11: left/right channels inverted [1:0] spdif: 00: left/right channels non inverted 11: left/right channels inverted 7654 3210 0000 delay_sw ls_l_r_sw r/w [7:4] reserved [3:2] delay output: 00: left/right channels non inverted 11: left/right channels inverted [1:0] loudspeaker l/r output: 00: left/right channels non inverted 11: left/right channels inverted www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 register list 127/167 10.20 autostandard coefficients settings autostd_coeff_ctrl autostandard coefficients control address: fbh type: r/w reset: 0000 0001 autostd_coeff_index_msb autosta ndard coefficients index msb address: fch type: r/w reset: 0000 0000 autostd_coeff_index_lsb autosta ndard coefficients index lsb address: fdh type: r/w reset: 0000 0000 7654 3 210 0 0 0 0 0 0 autostd_coeff_ctrl[1:0] r/w [7:2] reserved [1:0] control the demod filter coefficients table settings: 00: no action 01: init coefficients to rom values 10: update coefficients with i 2 c values (set to 0 by dsp to acknowledge) 76543210 0000000 autostd_coe ff_index_msb r/w [7:1] reserved [0] fir coefficients table index (msb) 7654 3210 autostd_coeff_index_lsb[7:0] r/w [7:0] fir coefficients table index (lsb) www.datasheet.co.kr datasheet pdf - http://www..net/
register list stv82x8 128/167 autostd_coeff_value autostandard coefficient value address: feh type: r/w reset: 0000 0000 note: these four registers (autostd_c oeff_ctrl, autostd_coeff_index_msb, autostd_coeff_index_lsb and autostd_ coeff_value) can be used to change parameter settings for the following parts of channel 1 or channel 2: - channel carrier dco frequency (register carfqxx) - channel filter coefficients (registers firxcx) - pll baseband am/fm demodulators proportional and integral coefficients (registers acoeffx or bcoeffx) - demodulator mode selection (register demod_ctrl) - if agc control (agc_ctrl) - channel 2 symbol tracking loop parameters (register scoeff) - zweiton control (register zwt_ctrl) while keeping the autostandard function always active. new values for all parameters mentioned above are kept instead of the values automatically sent by the autostandard function. one application is for example to implement overmodulation recovery mode for any sound standard supported by the device (b/g, i, m/n, dk1, dk2, or dk3). see technical note for instructions on how to update the coefficient table settings. patch_version patch version address: ffh type: r/w reset: 0000 0000 76543210 autostd_coeff_value[7:0] r/w [7:0] fir coefficients table value to update 7654521 0 patch_version[7:0] r/w [7:0] indicates the patch version which has been loaded in the device (can be used to check if the patch has been correctly loaded) www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 pin descriptions 129/167 11 pin descriptions 11.1 tqfp 80-pin package ap = analog power dp = digital power i= input o = output od = open-drain b = bi-directional a = aalog table 19. tqfp80 pin description pin no. stv82x8 pin name type (stv82x8) function for stv82x8 (function for stv82x6 in italic characters) stv82x6 pin name 1 sc1_out_l a scart1 audio output left ao1l 2 sc1_out_r a scart1 audio output right ao1r 3 vcc_h ap 8v power for audio i/o & esd not connected 4 gnd_h ap high current ground for audio outputs connected to ground 5 sc3_out_l a scart3 audio output left not connected 6 sc3_out_r a scart3 audio output right not connected 7 vcc33_sc ap 3.3v power for audio buffers & dac / adc vddc 8 gnd33_sc ap ground for audio buffers & dac / adc gndc 9 sc1_in_l a scart1 audio input left ai1l 10 sc1_in_r a scart1 audio input right ai1r 11 vrefa a audio bias voltage decoupling 1.55v (switched v ref decoupling pin for audio converters (vmcp)) vmc1 12 nc (gnd_sa in stv82x7 ) ap connected to ground 13 vbg a bandgap voltage reference decoupling 1.2v (v ref decoupling pin for audio converters (vmc)) vmc2 14 sc2_in_l a scart 2 audio input left ai2l 15 sc2_in_r a scart 2 audio input right ai2r 16 vcc33_ls ap 3.3v power for audio dacs (3.3v power supply for audio buffers and scart) vdda 17 gnd33_ls ap ground for audio dacs (ground for audio buffers and scart) gndah 18 sc2_out_l a scart 2 audio output left ao2l 19 sc2_out_r a scart 2 audio output right ao2r www.datasheet.co.kr datasheet pdf - http://www..net/
pin descriptions stv82x8 130/167 20 gnd_sa (vcc_niso in stv82x7 ) ap ground for dacs vddh 21 vss33_conv ap ground for dac 1.8 to 3.3v converters connected to ground 22 vdd33_conv ap 3.3v power for dac 1.8 to 3.3v converters (voltage reference for audio buffers) vrefa 23 sc3_in_l a scart 3 audio input left ai3l 24 sc3_in_r a scart 3 audio input right ai3r 25 scl_flt a scart filtering left not connected 26 scr_flt a scart filtering right (bandgap voltage source decoupling) bgap 27 ls_c a center output not connected 28 ls_l a left loudspeaker output lsl 29 ls_r a right loudspeaker output lsr 30 ls_sub a subwoofer output sw 31 hp_lss_l a left headphone output or left surround output hpl 32 hp_lss_r a right headphone output or right surround output hpr 33 vss18_conv dp ground for digital part of the dac/adc (substrate analog/digital shield) gndsa 34 vdd18_conv dp 1.8v power for digita l part of the dac/adc not connected 35 hp_det i headphone detection hpd 36 adr_sel i hardware address selection for i2c bus adr 37 vss18 dp ground for digital part connected to ground 38 vdd18 dp 1.8v power for digital part not connected 39 scl od i2c clock input scl 40 sda od i2c data i/o sda 41 vss18 dp ground for digital part connected to ground 42 vdd18 dp 1.8v power for digital part (5v power regulator control) reg 43 rst_n i main reset input reset 44 s/pdif_in i serial audio data input (system clock output) sysck 45 s/pdif_out o serial audio data output (i2s master clock output) mck 46 vdd33_io1 dp 3.3v power for digital io vdd1 47 vss33_io1 dp ground for digital io gnd1 table 19. tqfp80 pin description (continued) pin no. stv82x8 pin name type (stv82x8) function for stv82x8 (function for stv82x6 in italic characters) stv82x6 pin name www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 pin descriptions 131/167 48 ck_tst_ctrl d to be grounded not connected 49 vss18 dp ground for digital part gndsp 50 vdd18 dp 1.8v power for digital part not connected 51 clk_sel i clock input format selection not connected 52 xtalin_clkxtp i crystal oscillator input or differential input positive (crystal oscillator input) xti 53 xtalout_clkx tm o crystal oscillator output or differential input negative (crystal oscillator output) xto 54 vcc18_clk1 ap 1.8v power for clock pll analog & crystal oscillator 1/2 (3.3v power supply for analog pll clock) vddp 55 gnd18_clk1 ap ground for clock pll analog & crystal oscillator 1/2 gndp 56 gnd18_clk2 dp ground for clock pll digital 1/2 gnd2 57 vcc18_clk2 dp 1.8v power for clock pll digital 1/2 (3.3v power supply for digital core, dsps & io cells) vdd2 58 vss33_io2 dp ground for digital io connected to ground 59 vdd33_io2 dp 3.3v power for digital io not connected 60 i2s_pcm_clk i/o i2s master clock input /output channel 0, 1 & 2 not connected 61 i2s_sclk i/o i2s serial clock input/output channel 0, 1& 2 (i2s bus data output) sdo 62 i2s_lr_clk i/o i2s word select input/output channel 0, 1 & 2 (stereo detection output / i2s bus data input) st/sdi 63 i2s_data0 i/o i2s data input/output stereo channel 0 (i2s bus word select output) ws 64 i2s_data1 i i2s data input stereo channel 1 (i2s bus clock output) sck 65 i2s_data2 i i2s data input stereo channel 2 (bus expander output 1) bus1 66 vdd18 dp 1.8v power for digital core & i/o cells pin not connected 67 vss18 dp ground for digital core & i/o cells pin connected to ground 68 bus_exp o bus expander function (bus expander output 2) bus0 69 irq o interrupt request to microprocessor irq 70 gnd_psub ap ground substrate connection connected to ground 71 vdd18_adc dp vdd 1.8v for adc (digital part) not connected 72 vss18_adc dp ground to complement 1.8v vdd for adc connected to ground 73 sif_p a sound if input sif table 19. tqfp80 pin description (continued) pin no. stv82x8 pin name type (stv82x8) function for stv82x8 (function for stv82x6 in italic characters) stv82x6 pin name www.datasheet.co.kr datasheet pdf - http://www..net/
pin descriptions stv82x8 132/167 11.2 tqfp 100-pin package ap = analog power dp = digital power i= input o = output od = open-drain b = bi-directional a = analog 74 sif_n a adc v top decoupling pin vtop 75 gndpw_if ap polarization for the if block (voltage reference for agc decoupling pin) vrefif 76 vcc18_if ap 1.8v power for if agc & adc vddif 77 gnd18_if ap ground for if agc & adc gndif 78 mono_in a mono input (for am mono) monoin 79 sc4_in_l a scart4 audio input left not connected 80 sc4_in_r a scart4 audio input right not connected table 19. tqfp80 pin description (continued) pin no. stv82x8 pin name type (stv82x8) function for stv82x8 (function for stv82x6 in italic characters) stv82x6 pin name table 20. tqfp100 pin description pin no. stv82x8 pin name type (stv82x8) function for stv82x8 1 sc1_out_l a scart1 audio output left 2 sc1_out_r a scart1 audio output right 3 vcc_h ap 8v power for audio i/o & esd 4 gnd_h ap high current ground for audio outputs 5 sc3_out_l a scart3 audio output left 6 sc3_out_r a scart3 audio output right 7 vcc33_sc ap 3.3v power for audio buffers & dac / adc 8 gnd33_sc ap ground for audio buffers & dac / adc 9 sc1_in_l a scart1 audio input left 10 sc1_in_r a scart1 audio input right 11 vrefa a audio bias voltage decoupling 1.55v 12 vbg a bandgap voltage reference decoupling 1.2v 13 sc2_in_l a scart 2 audio input left 14 sc2_in_r a scart 2 audio input right www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 pin descriptions 133/167 15 vcc33_ls ap 3.3v power for audio dacs 16 gnd33_ls ap ground for audio dacs 17 sc2_out_l a scart 2 audio output left 18 sc2_out_r a scart 2 audio output right 19 sc5_in_l a scart 5 audio input left 20 sc5_in_r a scart 5 audio input right 21 nc not to be connected 22 nc not to be connected 23 gnd_sa ap ground for dacs 24 nc not to be connected 25 nc not to be connected 26 vss33_conv ap ground for dac 1.8 to 3.3v converters 27 vdd33_conv ap 3.3v power for dac 1.8 to 3.3v converters 28 sc3_in_l a scart 3 audio input left 29 sc3_in_r a scart 3 audio input right 30 scl_flt a scart filtering left 31 scr_flt a scart filtering right 32 ls_c a center output 33 nc not to be connected 34 ls_l a left loudspeaker output 35 nc not to be connected 36 ls_r a right loudspeaker output 37 nc not to be connected 38 ls_sub a subwoofer output 39 nc not to be connected 40 hp_lss_l a left headphone output or left surround output 41 nc not to be connected 42 hp_lss_r a right headphone output or right surround output 43 nc not to be connected 44 nc not to be connected 45 vss18_conv dp ground for digital part of the dac/adc 46 vdd18_conv dp 1.8v power for digital part of the dac/adc 47 hp_det i headphone detection 48 adr_sel i hardware address selection for i2c bus table 20. tqfp100 pin description (continued) pin no. stv82x8 pin name type (stv82x8) function for stv82x8 www.datasheet.co.kr datasheet pdf - http://www..net/
pin descriptions stv82x8 134/167 49 vss18 dp ground for digital part 50 vdd18 dp 1.8v power for digital part 51 scl od i2c clock input 52 sda od i2c data i/o 53 rst_n i main reset input 54 i2sd_data i i2s data delay input stereo channel 55 i2so_data1 o i2s data output stereo channel o_1 56 i2so_lr_clk o i2s word select output channel o_0 & o_1 57 i2so_sclk o i2s serial clock output channel o_0 & o_1 58 i2so_datao o i2s data output stereo channel o_0 59 s/pdif_in i serial audio data input 60 s/pdif_out o serial audio data output 61 vdd33_io1 dp 3.3v power for digital io 62 vss33_io1 dp ground for digital io 63 ck_tst_ctrl d to be grounded 64 vss18 dp ground for digital part 65 vdd18 dp 1.8v power for digital part 66 clk_sel i clock input format selection 67 xtalin_clkxtp i crystal o scillator input or diff erential input positive 68 xtalout_clkxtm o crystal oscillator output or different ial input negative 69 vcc18_clk1 ap 1.8v power for clock p ll analog & crystal oscillator 1/2 70 gnd18_clk1 ap ground for clock pll analog & crystal oscillator 1/2 71 gnd18_clk2 dp ground for clock pll digital 1/2 72 vcc18_clk2 dp 1.8v power for clock pll digital 1/2 73 vss33_io2 dp ground for digital io 74 vdd33_io2 dp 3.3v power for digital io 75 i2s_pcm_clk i/o i2s master clock input/output channel 0, 1 & 2 76 i2s_sclk i/o i2s serial clock input/output channel 0, 1 & 2 77 i2s_lr_clk i/o i2s word select input/output channel 0,1 & 2 78 i2s_data0 i/o i2s data input/output stereo channel 0 79 i2s_data1 i i2s data input stereo channel 1 80 i2s_data2 i i2s data input stereo channel 2 81 nc not to be connected 82 nc not to be connected table 20. tqfp100 pin description (continued) pin no. stv82x8 pin name type (stv82x8) function for stv82x8 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 pin descriptions 135/167 note: pins indicated as not to be connected should have no connection at all even to ground. 83 nc not to be connected 84 nc not to be connected 85 vdd18 dp 1.8v power for digital core & i/o cells pin 86 vss18 dp ground for digital core & i/o cells pin 87 bus_exp o bus expander function 88 irq o interrupt request to microprocessor 89 gnd_psub ap ground substrate connection 90 vdd18_adc dp vdd 1.8v for adc (digital part) 91 vss18_adc dp ground to complement 1.8v vdd for adc 92 sif_p a sound if input 1 93 sif_n a adc v top decoupling pin 94 sif2_p a sound if input 2 95 gndpw_if ap polarization for the if block 96 vcc18_if ap 1.8v power for if agc & adc 97 gnd18_if ap ground for if agc & adc 98 mono_in a mono input (for am mono) 99 sc4_in_l a scart 4 audio input left 100 sc4_in_r a scart 4 audio input right table 20. tqfp100 pin description (continued) pin no. stv82x8 pin name type (stv82x8) function for stv82x8 www.datasheet.co.kr datasheet pdf - http://www..net/
application diagrams stv82x8 136/167 12 application diagrams figure 29. stv82x8 tqfp80 application diagram www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 application diagrams 137/167 figure 30. stv82x8 tqfp100 application diagram www.datasheet.co.kr datasheet pdf - http://www..net/
application diagrams stv82x8 138/167 figure 31. stv82x7/stv82x8 tqfp80 co mpatibility application diagram www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 input/output groups 139/167 13 input/output groups pin numbers apply to tqfp80 package only. vcc18_if 50k gnd_psub sif_p73 50k 50k vcc18_if vcc33_ls gnd 33_ls 78 mono_in 30k vrefa vcc_h gnd_psub sc1_outl 1 2 5 6 18 19 sc1_outr sc2_outl sc2_outr sc3_outl sc3_outr vcc18_if gndif 74 sif_n vcc18_if ref vcc33_ls gnd_psub ls_c ls_l ls_r scr_flt ls_sub 25 ls_l hp_lss_l hp_lss_r 26 27 28 29 30 31 32 150 vcc_h gnd_psub 9 sc1_in_l 22k5 7k5 vrefa 10 14 15 23 24 79 80 sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r sc4_in_l sc4_in_r www.datasheet.co.kr datasheet pdf - http://www..net/
input/output groups stv82x8 140/167 vcc33_ls 5k4 gnd33_ls 16k8 11 vrefa vb g (1.2v) vcc33_ls gnd33_ls 13 vb g 10k band-gap=1.2v vdd33_i02 vcc18_clk1 vdd33_i01 gnd_psub gnd18_clk2 gnd18_clk1 vss 21 59 46 54 56 55 37 57 vcc18_clk2 vdd18 38 42 50 66 41 47 49 58 67 70 vss 35 hp_det 36 43 adr_sel rst_n vdd33_i01 clk_tst_ctrl 48 vss 45 s/pdif_out vdd33_i01 vdd33_i01 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 input/output groups 141/167 vss bus_exd vdd33_i02 vdd33_i02 irq 68 69 53 xtalout_clkxtm 52 xtalin_clkxtp vcc18_clk1 500k gnd18_clk1 vcc18_clk1 gnd18_clk1 vss 44 s/pdif_in vdd33_i01 vss 51 clk_sel vdd18 vss 60 i2s_pcm_clk 61 62 i2s_lr_clk i2s_data0 vdd33_i02 i2s_data1 63 64 i2s_data2 vss 35 scl 40 sda www.datasheet.co.kr datasheet pdf - http://www..net/
input/output groups stv82x8 142/167 vdd18_conv 34 vdd33_conv 22 vcc_niso 20 vcc33_ls 16 vcc33_sc 7 vcc_h 3 vdd18_adc 71 vcc18_if 76 gnd18_if 77 gndpw_if 75 vss18_adc 72 gnd_psub 70 gnd33_ls 17 gnd_h 4 gnd33_sc 8 gnd_sa 12 vss18_conv 33 21 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 general description 143/167 14 general description this chip performs btsc stereo and sap analog tv stereo sound identification and demodulation (no specific i2c programming is required). it offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround effects. it provides a cost-effective solution for analog and digital tv designs. the stv82x8 is an audio processor which integrates srs ? ? wow tm , srs? trusurround xt tm , dolby ? ? pro logic ? ? dolby ? ? pro logic ii ? ? virtual dolby ? ? surround (vds) and virtual dolby ? ? digital (vdd) capabilities. advanced st royalty-free algorithms such as st omnisurround tm , st widesurround tm , st dynamic bass tm are also available in this audio sound processor. st omnisurround tm is a certified dolby ? ?? algorithm for the virtual dolby ? ? digital (vdd) and the virtual dolby ? ? surround (vds). when using vdd or vds, either an external dolby ? ? digital or an internal pro logic ? ? (or pro logic ii ? ) decoder must be used respectively. the stv82x8 is perfectly suited to current and future digital tv platforms, based on audio/video digital chips (std2000 - dtv100 plat form) which include an internal digital decoder (mpeg, dolby ? ? digital...). in the case where a dolby ? ? digital decoder is embedded in the audio/video digital chip, virtual dolby ? ? digital certification could be obtained. table 21. stv8x8 version list (tqfp 80) s t v 8 2 1 8 s t v 8 2 3 8 STV8248 stv8258 stv8268 stv8278 stv8288 s t v 8 2 4 8 d s t v 8 2 4 8 d s x s t v 8 2 5 8 d s t v 8 2 5 8 d s x s t v 8 2 5 8 s x s t v 8 2 6 8 d s t v 8 2 6 8 d s x s t v 8 2 7 8 d s t v 8 2 7 8 d s x s t v 8 2 8 8 d s t v 8 2 8 8 d s x demodulation btsc & dbx noise reduction xxxxxx xxxxxxx multi-channel capabilities analog loudspeakers output number 2.1 2.1 2.1 2.1 2.1 2.1 2.1 5.1 5.1 5.1 5.1 5.1 5.1 i2s in (exclusive with i2s out) 11 1 1 3 3 3113333 s/pdif (pass-thru or output) 11 1 1 1 1 1111111 virtual dolby ? surround xxxx xxxx vds plii vds plii www.datasheet.co.kr datasheet pdf - http://www..net/
general description stv82x8 144/167 virtual dolby ? digital capability (1) x x x xxxx dolby ? pro logic ? (dpli) or dolby ? pro logic ii ? (dplii) dpli (inter nal) dpli (inter nal) dpli (inter nal) dpli (inter nal) dpl i dpl i dpl i dpl i dpl ii dpl ii audio processing srs ? wow ? (wow) x srs ? trusurround xt tm x xxxxx st voice tm , st dynamic bass tm xxxxxx xxxxxxx st widesurround tm st omnisurround tm (2) xxxxxx xxxxxxx 1. dolby ? digital bypass capability or virtual dolby ? digital are obtained with the use of an external dolby ? digital decoder (for example std2000) 2. when using virtual dolby ? digital or virtual dolby ? surround with st omnisurround tm or srs ? trusurround xt tm a dolby ? digital or a pro logic ? (or pro logic ii ? ) decoder is mandatory respectively table 22. stv82x8 version list (tqfp 100) s t v 8 2 1 8 f s t v 8 2 3 8 f STV8248 stv8258 stv8268 stv8278 stv8288 s t v 8 2 4 8 f d s t v 8 2 4 8 f d s x s t v 8 2 5 8 f d s t v 8 2 5 8 f d s x s t v 8 2 5 8 f s x s t v 8 2 6 8 f d s t v 8 2 6 8 f d s x s t v 8 2 7 8 f d s t v 8 2 7 8 f d s x s t v 8 2 8 8 f d s t v 8 2 8 8 f d s x demodulation btsc & dbx noise reduction xx x x x x xxxxxxx table 21. stv8x8 version list (tqfp 80) (continued) s t v 8 2 1 8 s t v 8 2 3 8 STV8248 stv8258 stv8268 stv8278 stv8288 s t v 8 2 4 8 d s t v 8 2 4 8 d s x s t v 8 2 5 8 d s t v 8 2 5 8 d s x s t v 8 2 5 8 s x s t v 8 2 6 8 d s t v 8 2 6 8 d s x s t v 8 2 7 8 d s t v 8 2 7 8 d s x s t v 8 2 8 8 d s t v 8 2 8 8 d s x www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 general description 145/167 multi-channel capabilities analog loudspeakers output number 2.1 2.1 2.1 2.1 2.1 2.1 2.1 5.1 5.1 5.1 5.1 5.1 5.1 i2s in 11 1 1 3 3 3113333 s/pdif (pass-thru or output) 11 1 1 1 1 1111111 2nd sif input x x x x x x x x x x x x x i2s output (always available) 11 1 1 1 1 1111111 virtual dolby ? surround xxxx xxxx vds plii vds plii virtual dolby ? digital capability (1) x x x xxxx dolby ? pro logic ? (dpli) or dolby ? pro logic ii ? (dplii) 5.1 output dpli (inter nal) dpli (inter nal) dpli (inter nal) dpli (inter nal) dpl i dpl i dpl i dpl i dpl ii dpl ii audio processing srs ? wow tm (wow) x srs ? trusurround xt tm x xxxxx st voice tm , st dynamic bass tm xx x x x x xxxxxxx st widesurround tm , st omnisurround tm (2) xx x x x x xxxxxxx 1. dolby ? digital bypass capability or virtual dolby ? digital are obtained with the use of an external dolby ? digital decoder (for example std2000). 2. when using virtual dolby ? digital or virtual dolby ? surround with st omnisurround tm or srs ? trusurround xt tm a dolby ? digital or a pro logic ? (or pro logic ii ? ) decoder is mandatory respectively table 22. stv82x8 version list (tqfp 100) (continued) s t v 8 2 1 8 f s t v 8 2 3 8 f STV8248 stv8258 stv8268 stv8278 stv8288 s t v 8 2 4 8 f d s t v 8 2 4 8 f d s x s t v 8 2 5 8 f d s t v 8 2 5 8 f d s x s t v 8 2 5 8 f s x s t v 8 2 6 8 f d s t v 8 2 6 8 f d s x s t v 8 2 7 8 f d s t v 8 2 7 8 f d s x s t v 8 2 8 8 f d s t v 8 2 8 8 f d s x www.datasheet.co.kr datasheet pdf - http://www..net/
general description stv82x8 146/167 14.1 stv82x8 overview 14.1.1 core features single audio source processing: ? if source and/or analog stereo input (scart) ? one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three i2s) sif input signal with automatic gain control (agc) btsc and sap demodulator, fm mono audio processor working at 48 khz with specific features: ? for loudspeakers (l, r, l s , r s , subw, c): dolby ? pro logic ii ? speakers (l, r, l s , r s , subw, c): dolby ? decoder with bass management srs ? wow tm or trusurround xt tm including virtual dolby ? surround and virtual dolby ? digital st widesurround tm st omnisurround tm st dynamic bass tm 5-band equalizer or bass / treble controls loudness svc (smart volume control) volume/balance/soft-mute three different types of bips video processing delay compensation ? for headphones: srs ? trubass tm st dynamic bass tm svc (smart volume control) bass/treble controls loudness volume/balance/soft-mute three different types of bips video processing delay compensation shared outputs for headphone and certain loudspeakers (surround channels); analog matrix with: ? five external inputs: four scart inputs (2 v rms capable) one analog mono input (0.5 v rms ) ? one internal input from a digital matrix via a dac ? three external outputs (2 v rms capable) ? one internal output for the digital matrix (using an internal adc) digital matrix with: ? three input modes (demodulator/scart, scart only and i2s) ? three stereo outputs (loudspeakers, headphone and scart) high-end audio dac www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 general description 147/167 s/pdif output for connection with an external amplifier/decoder internal multiplexer for the s/pdif output (to share the internal s/pdif output and the s/pdif output generated by the external decoder of the digital broadcast) specific stand-by mode (loop-through) control by i2c bus (two i2c addresses) system pll and clock generation using either a single crystal oscillator or a differential clock input 14.1.2 software information the different software combinations are listed in ta bl e 2 3 . note: 1 in addition to the above sound processing, it is always possible to add st voice tm and also st dynamic bass tm algorithms. 2 the srs ? trusurround ? and st omnisurround tm are approved by dolby ? labs as virtual dolby ? surround (vds) and virtual dolby ? digital (vdd). the srs ? trusurround xt tm system is composed of: srs ? trusurround tm srs ? wow tm the srs ? wow tm system also includes: srs ? dialog clarity tm srs ? trubass tm srs ? 3d mono/stereo tm table 23. input/output software configurations input (number of channels) output (number of channels) 2 (+1) 4 (+1) 5.1 1 (mono) st widesurround tm or srs ? wow tm 2 (l o & r o ) st widesurround tm or st omnisurround tm or srs ? trusurround xt tm or srs ? wow ? or dolby ? pro logic ? ii dolby ? pro logic ? ii dolby ? pro logic ? ii 2 (l t & r t ) st widesurround tm or st omnisurround tm or srs ? trusurround xt tm or srs ? wow tm or dolby ? pro logic ? i or ii dolby ? pro logic ? i or ii dolby ? pro logic ? ii 4 (+1) st omnisurround tm or srs ? trusurround xt tm no processing 5.1 st omnisurround tm or srs ? trusurround xt tm downmix no processing www.datasheet.co.kr datasheet pdf - http://www..net/
general description stv82x8 148/167 14.1.3 electrical features multi power supplies: 1.8 v, 3.3 v and 8 v. power consumption: lower than 800mw in functional mode (full features) 200 mw in loop-through mode corresponding to the switch-off of all digital blocks 14.2 typical applications the stv82x8 is specified to enable flexible, analog and digital tv chassis design (refer to figure 32 , figure 33 , figure 34 , and figure 35 ). the main considerations are: all necessary connections between devices can be provided through the tv set, pseudo stand-by mode used to copy to vcr or the dvd sources when the tv set is off, pin compatibility with previous stv82x7 (tqfp80 package) tv design. the stv82x8 can be used to process dual audio sources (one analog and one digital in parallel). note: headphone and loudspeakers can be used simultaneously for dual-language purpose. in this case, certain restrictions occur (see section 2.2: audio processing ). for more connections, the scart-to-scart path can be used. the use of these full analog paths implies that the sound is not digitally processed. figure 32. stv8238 typical application (enhanced stereo) or tu n e r stv8238 demodulation sound processing - volume, balance, 5-band equalizer - st omnisurround left right - btsc stereo & sap - srs ? wow ? r subw l 4 x scart (tqfp100) i2s in and out (tqfp100) i2s in or out (tqfp80) 4 x scart (tqfp100) s/pdif output & pass-thru www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 general description 149/167 figure 33. STV8248 typical application (analog virtual sound) figure 34. stv8258 typical application (digital virtual sound) or tuner STV8248 demodulation sound processing - volume, balance, 5-band equalizer left right - btsc stereo & sap - srs ? trusurround xt ? r subw l - virtual dolby ? surround 1 - st omnisurround ? 1. when using vds with st omnisurround ? or srs trusurround xt ? , an optional internal pro logic ? decoder is mandatory. i2s in and out (tqfp100) i2s in or out (tqfp80) 4 x scart (tqfp100) 4 x scart (tqfp100) s/pdif output & pass-thru or tuner stv8258 demodulation audio processing - volume, balance, 5-band equalizer - srs ? trusurround xt ? - virtual dolby ? surround 1 multi-channel digital decoder left right i2s - btsc stereo & sap s/pdif - virtual dolby ? digital 2 r subw l (dolby ? digital) - st omnisurround ? 1. when using vds with st omnisurround tm or srs trusurround xt tm , an optional internal pro logic ? decoder is mandatory. 2. when using vdd with st omnisurround tm or srs trusurround xt tm , an external dolby ? digital decoder is mandatory. output & pass-thru 4 x scart (tqfp100) www.datasheet.co.kr datasheet pdf - http://www..net/
general description stv82x8 150/167 figure 35. stv8288 typical application (digit al tv: multi-channel and virtual sound) figure 36. stv8218 typical application (dvd & hdd recorders) or tu n e r stv8288 demodulation audio processing - volume, balance, 5-band equalizer left right i2s - btsc stereo & sap - dolby ? pro logic ii ? - st omnisurround ? r subw l c l s r s - 5.1 analog outputs - srs ? trusurround xt ? - virtual dolby ? surround 1 multi-channel digital decoder (dolby ? digital) 1. when using vds with st omnisurround tm or srs trusurround xt tm , an optional internal pro logic ? decoder is mandatory. 2. when using vdd with st omnisurround tm or srs trusurround xt tm , an external dolby ? digital decoder is mandatory. 4 x scart (tqfp100) s/pdif output & pass-thru - virtual dolby ? digital 2 shared with surround l s /r s or tuner stv8218 demodulation left right - btsc stereo & sap a/v codec i2s (digital recorder) 4 x scart (tqfp100) - volume, balance, 5-band equalizer - st omnisurround tm www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 system clock 151/167 15 system clock the system clock integrates 2 independent frequency synthesizers. the first frequency synthesizer is used by the demodulator at a frequency of 24.576 mhz. the second frequency synthesizer is used by the dsp core and can be adjusted between 100 and 150 mhz depending on the application. the default values are designed for a standar d 27-mhz reference frequency provided by a stable single crystal oscillator or an external differential clock signal (for example, from the stv35x0) depending on the clk_sel pin confi guration (clk_sel = 1 means a single crystal oscillator, 0 means an external differential clock). the 27-mhz value is the recommended frequency for minimizing potential rf interference in the application. the sinusoidal clock frequency, and any harmonic products, remain outside the tv picture and sound ifs (pif/sif) and band-i rf. note: a change in the reference frequency is compatible with other default i2c programming values, including those of the built-in automatic standard recognition system. 16 digital demodulator the digital demodulator (see figure 37 ) consists of a channel demodulator and a stereo/sap decoder. all channel parameters are programmed automatically by the built-in automatic standard recognition system (autostandard) in order to find the stereo or the sap modes. channel parameters can also be programmed manually via the i2c interface for very specific standards not included among the known standards. figure 37. demodulator block diagram mixer channel filter fir1 fm demodulator agc control sif dco1+ a/d carfq1 (12-14h) agc amp stereo/sap demodulator (l+r)* or mono* (l-r)dbx or sapdbx dsp processing deemphasis, dbx decoding and dematrixing autostd detection demod_stat(0dh) stereo_sap_status(4ch ) fir1c (15-1ch) acoeff1(1dh) bcoeff1(1eh) sap_conf(47h) *: pre-emphasis signal dbx: dbx -encoded signal www.datasheet.co.kr datasheet pdf - http://www..net/
digital demodulator stv82x8 152/167 16.1 sound if signal the analog sound carrier if is connected to the stv82x8 via the sif pin. before adc (analog-to-digital conversion), an agc (automatic gain control) is performed to adjust the incoming if signal to the full scale of the adc. a preliminary video rejection is recommended to optimize conversion and demodulation performances. the agc system provides a gain value allowing for a wide range of sif input levels. the tqfp100 package provides a second sif input. 16.2 demodulation the demodulation system operates by default in automatic mode. in this mode, the stv82x8 is able to identify and demodulate the btsc tv sound standard including stereo and sap modes without any external control via the i2c interface. the built-in automatic standard recognition system (autostandard) automatically programs the appropriate bits in the i2c registers which are forced to read-only mode for users. stereo and sap modes can be removed (or added) from the list of modes to be recognized by programming registers autostd_ctrl. the identified standard is displayed in register autostd_status and any change to standard is flagged to the host system via pin irq. this flag must be reset by re-programming the lsb of register irq_status while checking the detected standard status by reading registers autostd_status . * fh = line frequency (1) l+r and l-r must not exceed 50 khz sound carrier frequency offset recovery: if carrier frequency can be adjusted with register caroffset1 within a large range (up to 120 khz ) while the automatic standard recognition system remains active. the frequency offset estimation is written in registers demod_dc_level and can be used to implement the automatic frequency control (afc) via an external i2 2 c control. manual mode: if required, the automatic standard recognition system system can be disabled (manual mode) and the user can contro l all registers including those only controlled by the automatic standard recognition system function when active. manual mode is table 24. btsc standard source modulation frequency range audio pre- processing sub-carrier modulation type sub-carrier deviation aural carrier (4.5 mhz) peak deviation mono l+r 0.05 -15 khz 75 s pre- emphasis 25 khz (1) pilot fh * 5khz stereo l-r 0.05 -15 khz dbx compression 2 x fh * am dsb sc 50 khz(1) sap 2nd channel 0.05 -15 khz dbx compression 5 x fh * fm 10 khz 15 khz www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 digital demodulator 153/167 selected in register autostd_ctrl by se tting to 0 bits sap_check, stereo_check and mono_check. www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics stv82x8 154/167 17 electrical characteristics test conditions: t oper = 25 c, v cc_h = 8 v, v xx_18 = 1.8v, v xx_33 = 3.3v, crystal oscillator at 27 mhz, default register values for synthesizer, unless otherwise specified 17.1 absolute maximum ratings 17.2 thermal data 17.3 power supply data symbol parameter value units v xx_18 analog and digital 1.8 v supply voltage (v cc18_clk1 , v cc18_clk2 , v cc18_if , v dd18 , v dd18_conv , v dd18_adc ) 2.5 v v xx_33 analog and digital 3.3 v supply voltage (v cc33_sc , v cc33_ls , v dd33_io1 , v dd33_io2 , v dd33_conv , v cc_niso ) 4.0 v hv cc analog supply high voltage (v cc_h )8.8v v esd capacitor 100 pf discharged via 1.5 k serial resistor (human body model) 4kv t oper operating ambient temperature 0, +70 c t stg storage temperature -55 to +150 c symbol parameter value units r thja junction-to-ambient thermal resistance 42 c/w symbol parameter min. typ. max. units v xx_18 analog and digital 1.8 v supply voltage (v cc18_clk1 , v cc18_clk2 , v cc18_if , v dd18 , v dd18_conv , v dd18_adc ) 1.70 1.80 1.90 v v xx_33 analog and digital 3.3 v supply voltage (v cc33_sc , v cc33_ls , v dd33_io1 , v dd33_io2 , v dd33_conv , v cc_niso ) 3.13 3.30 3.47 v hv cc analog supply high voltage (v cc_h ) 7.6 8.0 8.4 v i vdd18 current consumption for digital 1.8 v supply (v cc18_clk2 , v dd18 , v dd18_conv , v dd18_adc ) 210 ma i vdd33 current consumption for digital 3.3 v supply (v dd33_io1 , v dd33_io2 )10ma i vcc18 current consumption for analog 1.8 v supply (v cc18_clk1 , v cc18_if )50ma i vcc33 current consumption for analog 3.3 v supply (v cc33_sc , v cc33_ls , v dd33_conv , v cc_niso ) 70 ma www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 electrical characteristics 155/167 17.4 crystal oscillator 17.5 analog sound if signal i vcc_h current consumption for analog supply high voltage (8 v) 4 ma p dtot total power dissipation 760 mw symbol parameter min. typ. max. units symbol parameter min. typ. max. units f p crystal series resonance frequency (at c21 = c22 = 27 pf load capacitor) 27 mhz df/f p frequency tolerance at 25 c -30 +30 ppm df/f t frequency stability versus temperature within a range from 0 to 70 c -30 +30 ppm c1 motional capacitor 15 ff r s serial resistance 30 w c s shunt capacitance 7 pf symbol parameter test conditions min. typ. max. units band sif sif frequency flatness agc_err at 0, frequency range from 4 to 7mhz 0.6 3 db r insif sif input resistance 60 72 85 k dc insif sifinput dc level 0.9 v c insif sif input capacitance 3 pf fm carrier vsif fm sif input sensitivity snr 40 db rms unweighted 20 hz to 15 khz standard m/n 27 khz fm deviation 1 khz 350 v pp agc agc step if agc step 1.4 1.5 1.6 db agc dyn relative maximum gain to step 0 val id from step 21 to step 31 29 30 31 db www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics stv82x8 156/167 17.6 sif to i2s output path characteristics test conditions: sif amplitude = 100 mvpp, unless otherwise specified, i2s output . 17.7 scart to scart analog path characteristics test conditions: rload max = 10 k , cload max = 330 pf, mono_in voltage = 0.5 v rms symbol parameter test conditions min. typ. max. units fm demodulation band fm frequency response 20 hz to 14 khz 1 db snr fm signal to noise rms unweighted, 20 hz to 15 khz, standard m/n 27 khz fm deviation,1 khz 66 db thd fm total harmonic distortion 0.05 % sep fm stereo channel separation standard m/n btsc stereo, fm deviation, 1 khz 30 db symbol parameter test conditions min. typ. max. units analog-to-analog stereo and mono r inscart scart input resistance 34 k r outscart output resistance for scarts 40 w vdc inscar t scart input dc level 1.57 v vdc outsca rt scart output dc level 3.64 v clip scart clipping scart clipping input level from scart input at 1 khz 1% thd 2v rms clipping input level from mono_in input 0.5 v rms thd scart thd scart thd from scart input 1 v rms , at 1 khz 0.02 0.05 % thd from mono_in input 0.25 v rms , at 1 khz 0.02 0.05 % snr scart signal to noise ratio scart input 1 v rms, 20 hz to 20 khz bandwidth, rms unweighted 82 db mono_in input 0.25 v rms, 20 hz to 20 khz bandwidth, rms unweighted 76 db band scart frequency flatness scart input 20 hz to 20 khz -0.5 0 0.5 db mono_in input 20 hz to 20 khz 11.5 12 12.5 db www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 electrical characteristics 157/167 17.8 scart and mono in to i2s path characteristics test conditions: sampling frequency = 48 khz, maximum mono_in voltage = 0.5 v rms . 17.9 i2s to ls/hp/sub/c path characteristics test conditions: sampling frequency = 48khz, l load = 100 h, c load = 33nf, r load = 30k xtalk l/r left/right crosstalk 1v rms @ 1 khz on ref signal, the other one grounded 80 90 db xtalk in audio crosstalk fr om input channel n to input channel m 1v rms @ 1 khz on ref signal, all other inputs grounded 80 90 db xtalk out audio crosstalk from output channel n to output channel m 1v rms @ 1 khz on reference output, signal on a single input, all other inputs grounded 80 90 db symbol parameter test conditions min. typ. max. units symbol parameter test conditions min. typ. max. units thd adc thd adc thd from scart input v in = 2 v rms at 1 khz 0.006 0.05 % thd from mono_in input v in = 0.5 v rms at 1 khz 0.006 0.05 % snr adc signal to noise ratio 20 to 15 khz bandwidth, rms unweighted v in = 200 mv rms scart input 62 db band adc frequency flatness 20 hz to 15 khz 0.5 db xtalk adc left/right crosstalk at 1 khz, v in = 1 v rms 95 db symbol parameter test conditions min. typ. max. units r outdac output resistance for main outputs ls_l, ls_r, ls_sub, ls_c, hp_lss_r and hp_lss_l pins 90 140 w vdc outdac main output dc level 1.54 v thd dac total harmonic distortion 90% fu ll-scale range at 1 khz 0.06 % snr dac signal to noise ratio 20 to 15 khz bandwidth, rms unweighted, at -20db full range 75 db v outampda c main output amplitude 100% full -scale range at 1 khz 900 mv rm s xtalk dac left/right ccrosstalk a t 1 khz, -20dbfs 87 db www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics stv82x8 158/167 17.10 i2s to scart pa th characteristics test conditions: sampling frequency = 48 khz, c load = 33 nf on dac scart pins, dac scart prescale at -5.5 db . 17.11 mute characteristics 17.12 digital i/os characteristics symbol parameter test conditions min. typ. max. units thd dacscart total harmonic distortion 50% full-scale range at 1 khz 0.08 0.2 % snr dacscart signal to noise ratio 20 hz to 15 khz bandwidth unweighted, -20db full range 73 db v odacscart main output amplitude 100% full-scale range at 1 khz 2 v rms xtalk dacsca rt left/right crosstalk a t 1 khz, -20 dbfs 80 db symbol parameter test conditions min. typ. max. units mute dac dac mute analog i2s to dac at 1 khz 90 db mute scart scart mute 2v rms @ 1 khz on ref signal, all other inputs grounded 81 db symbol parameter test conditions min. typ. max. units v il low level input voltage except sda, scl and clk_sel, 3.3v power supply 0.5 v v ih high level input voltage except sda, scl and clk_sel, 3.3v power supply 2.0 v i in input current 1 a vil clk_sel clk_sel low level input voltage 1.8v power supply 0.3 v vih clk_sel clk_sel high level input voltage 1.8v power supply 1.2 v v ol low level output voltage s/pdif_out, irq, bus_exp 0.3 v v oh high level output voltage s/pdif_out, irq, bus_exp 3.0 v www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 electrical characteristics 159/167 17.13 i2c bus characteristics symbol parameter test conditions min. typ max. unit scl v il low level input voltage -0.3 1.5 v v ih high level input voltage 2.3 5.5 v i il input leakage current v in = 0 to 5.0 v -10 10 a f scl clock frequency 400 khz t r input rise time 1 v to 2 v 300 ns t f input fall time 2 v to 1 v 300 ns c i input capacitance 10 pf sda v il low level input voltage -0.3 1.5 v v ih high level input voltage 2.3 5.5 v i il input leakage current v in = 0 to 5.0 v -10 10 a t r input rise time 1 v to 2 v 300 ns t f input fall time 2 v to 1 v 300 ns v ol low level output voltage i ol = 3 ma 0.4 v t f output fall time 2 v to 1 v 250 ns c l load capacitance 400 pf c i input capacitance 10 pf i2c timing t low clock low period 1.3 s t high clock high period 0.6 s t su,dat data set-up time 100 ns t hd,dat data hold time 0 900 ns t su,sto set-up time from clock high to stop 0.6 s t buf start set-up time following a stop 1.3 s t hd,sta start hold time 0.6 s t su,sta start set-up time following clock low to high transition 0.6 s www.datasheet.co.kr datasheet pdf - http://www..net/
electrical characteristics stv82x8 160/167 figure 38. i2c bus timing 17.14 i2s bus interface i2s bus interface timing values shown in figure 39 . t buf t low t high t hd,sta t r t f t su,sta t hd,dat t su,dat t su,sto sda scl sda symbol parameter test conditions min. typ. max. unit i2s input v i2s_il input i2s low level voltage 0.8 v v i2s_ih input i2s high level voltage 2 v z i2s input i2s impedance 5 pf i i2s_leak i2s leakage current -1 1 a t i2s_su i2s input setup time before rising edge of clock see figure 39 30 ns t i2s_ho i2s input hold time after rising edge of clock see figure 39 100 ns f i2s_lr0 i2s left/right strobe input frequency (i2s_data0 with src) 30 49 khz f i2s_scl0 i2s serial clock input frequency (i2s_data0 with src) 1.092 3.136 mhz f i2s_lr i2s left/right strobe input frequency (i2s_data0 with pll, i2s_data1,2) deviation = 250 ppm 48 khz f i2s_scl i2s serial clock input frequency (i2s_data0 with pll, i2s_data1,2) 3.072 mhz r i2s_scl i2s serial clock input ratio 0.9 1.1 www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 electrical characteristics 161/167 figure 39. is input bus timings i2s output (i2s_data0 only) v i2sol output i2s low level voltage i ol = 2 ma 0.4 v v i2soh output i2s high level voltage i oh = 2 ma 2.4 v f i2s_olr i2s left/right strobe output frequency (i2s_data0 and i2so_data0,1) 48 khz f i2s_oscl i2s serial clock output frequency (i2s_data0 and i2so_data0,1) 3.072 mhz r i2s_scl i2s serial clock output ratio 0.9 1.1 t i2s_del i2s output delay after falling edge of clock see figure 39 , cl = 30 pf 30 ns symbol parameter test conditions min. typ. max. unit i2s_sclk i2s_data t i2s_su t i2s_ho t i2s_su i2s_lr_clk www.datasheet.co.kr datasheet pdf - http://www..net/
package mechanical data stv82x8 162/167 18 package mechanical data 18.1 tqfp80 package figure 40. 80-pin thin plastic flat package table 25. package mechanical dimensions dim. mm inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.009 0.013 0.015 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.65 0.026 a a2 a1 b e h c l l1 e e1 d1 d www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 package mechanical data 163/167 18.2 tqfp100 package figure 41. 100-pin thin plastic quad flat package k 0 3.5 0.75 0 3.5 0.75 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 e 0.65 0.026 k 0 3.5 0.75 0 3.5 0.75 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 table 25. package mechanical dimensions (continued) h c l l 1 e b a a 2 a1 d d1 e e 1 package mechanical dimensions dim. mm inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 www.datasheet.co.kr datasheet pdf - http://www..net/
package mechanical data stv82x8 164/167 18.3 environmentally-friendly packages in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 100 package mechanical dimensions (continued) www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 order information 165/167 19 order information note: for example : stv8258dsx/t will be delivered in a tqfp80 package with tape & reel conditioning table 26. order codes part number package conditioning stv82x8 tqfp80 tray stv82x8/t tqfp80 tape & reel stv82x8f tqfp100 tray stv82x8f/t tqfp100 tape & reel www.datasheet.co.kr datasheet pdf - http://www..net/
revision history stv82x8 166/167 20 revision history table 27. document revision history date revision changes 15-nov-2004 0.1 initial release. 19-nov-2004 0.2 major updates to features , and general description 07-jan-2005 0.3 addition of tqfp100 information 23-feb-2005 1.0 updated figure 1: stv82x8 block diagram (tqfp80) , figure 2: stv82x8 block diagram (tqfp100) , section 17.5: analog sound if signal and section 17.6: sif to i2s output path characteristics 01-jun-2006 1.1 reorder ing of chapters 31-mar-2009 2 preliminary banner removed, section 18.3: environmentally-friendly packages added www.datasheet.co.kr datasheet pdf - http://www..net/
stv82x8 167/167 please read carefully: information in this document is provided so lely in connection with st products. stmi croelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifi cations or improvements, to this docum ent, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and serv ices described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by est oppel or otherwise, to any intellectual pr operty rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or consider ed as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and cond itions of sale st disclaims any express or implied warranty with respect to the use and /or sale of st products includi ng without limi tation implied warranties of merch antability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an author ized st representative , st products are no t recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are no t specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions di fferent from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service descr ibed herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or regist ered trademarks of st in various countries. information in this document supersedes and r eplaces all informati on previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - h ong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - sw itzerland - united kingdom - united states of america www.st.com www.datasheet.co.kr datasheet pdf - http://www..net/

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